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* Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-180-0/+0
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| * Merge branch 'master' of https://github.com/ahmedirfan1983/yosysAhmed Irfan2014-01-180-0/+0
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| * \ Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2014-01-1813-12/+451
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* | \ \ pmux2muxAhmed Irfan2014-01-187-9/+197
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| * | | Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-181-3/+3
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| * | | Added $bu0 cell to simlib.vClifford Wolf2014-01-181-0/+22
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| * | | Improved setundef random number generatorClifford Wolf2014-01-181-1/+1
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| * | | Added setundef commandClifford Wolf2014-01-172-0/+158
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| * | | Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-171-1/+6
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| * | | Added techlibs/common/pmux2mux.vClifford Wolf2014-01-172-1/+26
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* | | | verilog default options pullAhmed Irfan2014-01-172-34/+104
| | | | | | | | | | | | | | | | shift operator width issues
* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-174-7/+119
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| * | | Merge pull request #4 from cliffordwolf/masterAhmed Irfan2014-01-174-7/+119
| |\| | | | | | | | | | verilog defaults
| | * | Added verilog_defaults commandClifford Wolf2014-01-171-0/+66
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| | * | Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-171-0/+6
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| | * | Added select -assert-none and -assert-anyClifford Wolf2014-01-172-7/+47
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* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-172-0/+117
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| * | | Merge pull request #3 from cliffordwolf/masterAhmed Irfan2014-01-172-0/+117
| |\| | | | |/ | |/| memory_unpack
| | * Added automatic memid generation to memory_unpack commandClifford Wolf2014-01-171-2/+2
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| | * Added memory_unpack commandClifford Wolf2014-01-172-0/+117
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* | | slice error correctedAhmed Irfan2014-01-161-5/+5
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* | | width issuesAhmed Irfan2014-01-152-65/+88
| | | | | | | | | | | | dff cell for more than one registers
* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-154-15/+60
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| * | Merge pull request #2 from cliffordwolf/masterAhmed Irfan2014-01-154-15/+60
| |\| | | | | | | hierarchy
| | * Merge pull request #20 from mschmoelzer/masterClifford Wolf2014-01-141-0/+1
| | |\ | | | | | | | | Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
| | | * Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-141-0/+1
| | |/ | | | | | | | | | | | | | | | This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
| | * Added hierarchy -libdir optionClifford Wolf2014-01-141-4/+48
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| | * renamed LibertyParer to LibertyParserClifford Wolf2014-01-143-9/+9
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| | * Added "+" to list of liberty token charactersClifford Wolf2014-01-141-2/+2
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* | | BTOR backendAhmed Irfan2014-01-142-279/+334
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* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-147-72/+364
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| * | Merge pull request #1 from cliffordwolf/masterAhmed Irfan2014-01-141-5/+71
| |\| | | | | | | Added "opt_const -mux_undef"
| | * Added "opt_const -mux_undef"Clifford Wolf2014-01-141-5/+71
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| * Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-121-1/+1
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| * Improved performance of freduce input cone reductionClifford Wolf2014-01-041-23/+78
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| * Improved freduce performance on const signalsClifford Wolf2014-01-041-13/+63
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| * Performance improvements in freduce passClifford Wolf2014-01-031-27/+69
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| * More freduce cleanupsClifford Wolf2014-01-031-0/+24
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| * Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-031-1/+23
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| * Cleanups in freduce commandClifford Wolf2014-01-031-2/+5
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| * Fixed SAT and ConstEval undef handling for $pmux and $safe_pmuxClifford Wolf2014-01-032-10/+43
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| * Tiny cleanup in proc_mux.ccClifford Wolf2014-01-031-3/+0
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* | splitnet -driver featureAhmed Irfan2014-01-036-45/+343
|\| | | | | | | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
| * Added "splitnets -driver"Clifford Wolf2014-01-031-29/+96
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| * Use selection in freduce commandClifford Wolf2014-01-031-5/+20
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| * Another small freduce cleanup/bugfixClifford Wolf2014-01-031-1/+2
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| * Added "connect" commandClifford Wolf2014-01-032-0/+186
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| * More freduce cleanups and bugfixesClifford Wolf2014-01-031-11/+32
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| * Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-032-0/+8
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* | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-0343-873/+2070
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