iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	opt_expr: Remove -clkinv option, make it the default.	Marcelina Kościelnicka	2020-07-31	5	-18/+17
\| \| \| \| \|	Adds -noclkinv option just in case the old behavior was actually useful to someone.
*	synth_ice40: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	7	-390/+93
\| \| \| \| \| \| \| \| \|	The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
*	synth_xilinx: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	7	-887/+219
\| \| \| \| \| \| \| \| \|	The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
*	async2sync: Support all FF types.	Marcelina Kościelnicka	2020-07-30	3	-145/+208
\|
*	Add opt_dff pass.	Marcelina Kościelnicka	2020-07-30	12	-3/+1790
\|
*	verilog_backend: Add handling for all FF types.	Marcelina Kościelnicka	2020-07-30	1	-252/+134
\|
*	Merge pull request #2314 from YosysHQ/verifix_errorfix	Miodrag Milanović	2020-07-29	1	-1/+3
\|\ \| \| \| \|	Verific - prevent exit yosys due to stored error
\| *	Clear last error message	Miodrag Milanovic	2020-07-29	1	-1/+3
\|/
*	opt_expr: Fix handling of $_XNOR_ cells with A = B.	Marcelina Kościelnicka	2020-07-29	2	-1/+15
\| \| \| \|	Fixes #2311.
*	ffinit: Fortify the code a bit.	Marcelina Kościelnicka	2020-07-28	1	-24/+19
\| \| \| \| \|	This fixes handling of messy cases involving repeatedly setting and removing the same init bit.
*	Merge pull request #2301 from zachjs/for-loop-errors	clairexen	2020-07-28	1	-17/+19
\|\ \| \| \| \|	Clearer for loop error messages
\| *	Clearer for loop error messages	Zachary Snow	2020-07-25	1	-17/+19
\| \|
* \|	Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef	clairexen	2020-07-28	2	-1/+38
\|\ \ \| \| \| \| \| \|	equiv_induct: Fix up assumption for $equiv cells in -undef mode.
\| * \|	equiv_induct: Fix up assumption for $equiv cells in -undef mode.	Marcelina Kościelnicka	2020-07-27	2	-1/+38
\| \|/ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Before this fix, equiv_induct only assumed that one of the following is true: - defined value of A is equal to defined value of B - A is undefined This lets through valuations where A is defined, B is undefined, and the defined (meaningless) value of B happens to match the defined value of A. Instead, tighten this up to OR of the following: - defined value of A is equal to defined value of B, and B is not undefined - A is undefined
* \|	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	8	-39/+133
\| \| \| \| \| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* \|	intel_alm: increase abc9 -W	Dan Ravensloft	2020-07-26	2	-7/+7
\| \|
* \|	Merge pull request #2299 from zachjs/arg-loop	clairexen	2020-07-26	3	-0/+73
\|\ \ \| \|/ \|/\|	Avoid generating wires for function args which are constant
\| *	Avoid generating wires for function args which are constant	Zachary Snow	2020-07-24	3	-0/+73
\| \|
* \|	async2sync: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-53/+11
\| \|
* \|	memory_dff: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-12/+5
\| \|
* \|	proc_dlatch: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-28/+8
\| \|
* \|	pmux2shift: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-15/+4
\| \|
* \|	wreduce: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-37/+7
\| \|
* \|	techmap: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-41/+4
\| \|
* \|	shregmap: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-39/+10
\| \|
* \|	abc: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-25/+6
\| \|
* \|	dffinit: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-41/+7
\| \|
* \|	zinit: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	2	-45/+13
\| \|
* \|	dfflegalize: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-80/+25
\| \|
* \|	clk2fflogic: Support all FF types.	Marcelina Kościelnicka	2020-07-24	20	-324/+245
\| \|
* \|	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	Marcelina Kościelnicka	2020-07-24	4	-6/+88
\|/
*	Add utility module for representing flip-flops.	Marcelina Kościelnicka	2020-07-23	2	-0/+441
\|
*	memory_dff: recognize more dff cells	Marcelina Kościelnicka	2020-07-23	1	-11/+112
\|
*	Add utility module for dealing with init attributes.	Marcelina Kościelnicka	2020-07-23	2	-0/+147
\|
*	Merge pull request #2285 from YosysHQ/mwk/techmap-cellname	clairexen	2020-07-23	4	-1/+50
\|\ \| \| \| \|	techmap: Add _TECHMAP_CELLNAME_ special parameter.
\| *	techmap: Add _TECHMAP_CELLNAME_ special parameter.	Marcelina Kościelnicka	2020-07-21	4	-1/+50
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* \|	Merge pull request #2294 from Ravenslofty/intel_alm_timings	clairexen	2020-07-23	5	-78/+95
\|\ \ \| \| \| \| \| \|	intel_alm: add additional ABC9 timings
\| * \|	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	5	-78/+95
\| \| \|
* \| \|	Remove EXPLICIT_CARRY logic.	Keith Rothman	2020-07-23	3	-150/+2
\| \|/ \|/\| \| \| \| \| \| \| \| \| \| \|	The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* \|	Merge pull request #2215 from boqwxp/qbfsat-solver-options	clairexen	2020-07-21	4	-4/+45
\|\ \ \| \| \| \| \| \|	qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands
\| * \|	smtio: Emit `mode: start` options before `set-logic` command and any other ↵	Alberto Gonzalez	2020-07-20	1	-1/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	options after it. Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode.
\| * \|	smtio: Add support for parsing `yosys-smt2-solver-option` info statements.	Alberto Gonzalez	2020-07-20	1	-3/+10
\| \| \|
\| * \|	qbfsat: Add `-solver-option` option.	Alberto Gonzalez	2020-07-20	2	-1/+15
\| \| \|
\| * \|	smt2: Add `-solver-option` option.	Alberto Gonzalez	2020-07-20	1	-0/+13
\|/ /
* \|	Merge pull request #2282 from YosysHQ/claire/satunsat	clairexen	2020-07-20	2	-4/+4
\|\ \ \| \| \| \| \| \|	Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
\| * \|	Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc	Claire Wolf	2020-07-20	2	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* \| \|	celltypes: Fix EN port name for some FF types.	Marcelina Kościelnicka	2020-07-20	1	-4/+4
\|/ /
* \|	Merge pull request #2276 from YosysHQ/mwk/satgen-cc	clairexen	2020-07-20	3	-1166/+1190
\|\ \ \| \|/ \|/\|	satgen: Move importCell out of the header.
\| *	satgen: Move importCell out of the header.	Marcelina Kościelnicka	2020-07-19	3	-1166/+1190
\|/ \| \| \| \|	This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
*	Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix	Miodrag Milanović	2020-07-17	1	-2/+6
\|\ \| \| \| \|	sf2: Emit CLKINT even if -clkbuf not passed