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* Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1657-3403/+3432
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| * Merge pull request #1302 from mmicko/dfflibmap_regressionClifford Wolf2019-08-162-10/+10
| |\ | | | | | | DFFLIBMAP pass regression fix
| | * Regression in abc9Miodrag Milanovic2019-08-161-1/+1
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| | * Just needed IDs to be IdStringMiodrag Milanovic2019-08-161-9/+9
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| * | Do not use Verific in tests/various/write_gzip.ysClifford Wolf2019-08-161-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add missing NMUX to "abc -g" handlingClifford Wolf2019-08-161-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1299 from YosysHQ/eddie/cleanup2Clifford Wolf2019-08-1533-1188/+1181
| |\ | | | | | | More cleanup, more use of ID() inside passes/techmap
| | * FixEddie Hung2019-08-151-2/+2
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| | * Change signature of parse_blif to take IdStringEddie Hung2019-08-152-2/+2
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| | * ID(\\.*) -> ID(.*)Eddie Hung2019-08-1525-766/+766
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| | * Convert a few more to IDEddie Hung2019-08-151-20/+20
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| | * Transform all "\\*" identifiers into ID()Eddie Hung2019-08-1525-782/+782
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| | * Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-1524-367/+362
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| | * More use of IdString::in()Eddie Hung2019-08-157-40/+38
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| * Merge pull request #1297 from YosysHQ/eddie/fix_1284_againEddie Hung2019-08-151-2/+2
| |\ | | | | | | extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR
| | * Merge remote-tracking branch 'origin/master' into eddie/fix_1284_againEddie Hung2019-08-1525-2240/+2275
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| * | Merge pull request #1275 from YosysHQ/clifford/idsClifford Wolf2019-08-1523-2205/+2269
| |\ \ | | | | | | | | New ID() macro and now also use it
| | * \ Merge branch 'master' into clifford/idsClifford Wolf2019-08-155-126/+244
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| * | | Merge pull request #1295 from YosysHQ/eddie/fix_travisClifford Wolf2019-08-152-35/+6
| |\ \ \ | | | | | | | | | | Fix Travis CI
| | * | | Revert earliest to gcc-4.8, compile iverilog with default compilerEddie Hung2019-08-142-3/+3
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| | * | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"Eddie Hung2019-08-141-5/+3
| | | | | | | | | | | | | | | | | | | | This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.
| | * | | Remove .0 from clang-8.0Eddie Hung2019-08-141-2/+2
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| | * | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!Eddie Hung2019-08-141-3/+5
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| | * | | bionic -> xenial as its on whitelistEddie Hung2019-08-141-1/+1
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| | * | | Bump gcc from 4.8 to 4.9 as undefined referenceEddie Hung2019-08-141-36/+7
| |/ / / | | | | | | | | | | | | | | | | ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
| | * | Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-112-2/+25
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-1110-1160/+1182
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | More improvements and cleanups in IdString subsystemClifford Wolf2019-08-113-43/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Use ID() macro in all of passes/opt/Clifford Wolf2019-08-1112-998/+998
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was obtained by running the following SED command in passes/opt/ and then using "meld foo.cc foo.cc.orig" to manually fix all resulting compiler errors. sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improve API of ID() macroClifford Wolf2019-08-111-2/+10
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * AND with an inverted input, causes X{,N}OR output to be inverted tooEddie Hung2019-08-141-2/+2
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| | | * Revert "Only sort leaves on non-ANDNOT/ORNOT cells"Eddie Hung2019-08-141-7/+6
| | | | | | | | | | | | | | | | This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400.
| | | * Only sort leaves on non-ANDNOT/ORNOT cellsEddie Hung2019-08-141-6/+7
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| * | Merge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284Eddie Hung2019-08-141-4/+8
| |\ \ | | | | | | | | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
| | * | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"Eddie Hung2019-08-141-4/+8
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| * | Merge pull request #1288 from YosysHQ/eddie/fix_1284Eddie Hung2019-08-131-8/+4
| |\ \ | | | | | | | | Since $_ANDNOT_ is not symmetric, do not sort leaves
| | * | Since $_ANDNOT_ is not symmetric, do not sort leavesEddie Hung2019-08-121-8/+4
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* | | README updatesMarcin Kościelnicki2019-08-131-0/+14
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* | | move attributes to wiresMarcin Kościelnicki2019-08-138-311/+546
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* | | minor review fixesMarcin Kościelnicki2019-08-132-3/+5
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* | | review fixesMarcin Kościelnicki2019-08-134-47/+34
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* | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-1310-93/+577
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | Merge pull request #1152 from 1138-4EB/feat-dockerSerge Bazanski2019-08-121-25/+49
|\ \ | | | | | | Dockerfile
| * | dockerfile: use 'python:3-slim-buster' base image1138-4EB2019-08-071-5/+8
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| * | dockerfile: use PREFIX instead of cp1138-4EB2019-08-071-5/+8
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| * | dockerfile: add ARG IMAGE, use three stages1138-4EB2019-08-071-13/+27
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| * | dockerfile: reduce number of COPY layers1138-4EB2019-08-071-7/+4
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| * | dockerfile: DEBIAN_FRONTEND should not be permanent1138-4EB2019-08-071-9/+16
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* | | Merge pull request #1277 from YosysHQ/eddie/fix_1262Eddie Hung2019-08-112-66/+189
|\ \ \ | |_|/ |/| | opt_expr -fine to now trim LSBs of $alu cells too
| * | Merge remote-tracking branch 'origin/master' into eddie/fix_1262Eddie Hung2019-08-1191-640/+759
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