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* Bump versionYosys Bot2020-10-231-1/+1
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* nexus: Add make_transp to BRAMsDavid Shah2020-10-221-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
|\ | | | | sim -vcd: add date, version, and option for timescale
| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
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| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
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| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
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* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-222-0/+32
| | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* | Bump versionYosys Bot2020-10-221-1/+1
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* | btor: Use Mem helper.Marcelina Kościelnicka2020-10-211-93/+102
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* | smt2: Use Mem helper.Marcelina Kościelnicka2020-10-211-186/+244
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* | verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
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* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
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* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
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* | opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
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* | memory_bram: Use Mem helpers.Marcelina Kościelnicka2020-10-211-121/+90
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* | memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
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* | memory_unpack: Use Mem helpers.Marcelina Kościelnicka2020-10-211-106/+10
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* | memory_collect: Use Mem helpers.Marcelina Kościelnicka2020-10-211-223/+9
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* | memory_nordff: Use Mem helpers.Marcelina Kościelnicka2020-10-211-63/+9
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* | Add new helper structures to represent memories.Marcelina Kościelnicka2020-10-213-1/+516
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* | Bump versionYosys Bot2020-10-211-1/+1
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* | Merge pull request #2405 from byuccl/fix_xilinx_cellsclairexen2020-10-201-2/+2
|\ \ | | | | | | xilinx/cells_sim.v: Move signal declaration to before first use
| * | Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
| | | | | | | | | | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
* | | Merge pull request #2404 from YosysHQ/claire/fixrpcargsclairexen2020-10-201-1/+2
|\ \ \ | | | | | | | | Fix argument handling in connect_rpc
| * | | Fix argument handling in connect_rpcClaire Xenia Wolf2020-10-191-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* | | | Bump versionYosys Bot2020-10-201-1/+1
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* | | Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1930-0/+12528
|\ \ \ | |_|/ |/| | synth_nexus: Initial implementation
| * | synth_nexus: Initial implementationDavid Shah2020-10-1530-0/+12528
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Bump versionYosys Bot2020-10-161-1/+1
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* | | Merge pull request #2398 from jakobwenzel/smtbmc-escapeclairexen2020-10-151-11/+29
|\ \ \ | | | | | | | | smtbmc: escape identifiers in verilog testbench
| * | | smtbmc: escape identifiers in verilog testbenchJakob Wenzel2020-10-061-11/+29
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* | | | Bump versionYosys Bot2020-10-131-1/+1
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* | | | extend verific library API for formal apps and generatorsMiodrag Milanovic2020-10-121-15/+83
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* | | | Bump versionYosys Bot2020-10-091-1/+1
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* | | | opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-082-8/+94
|/ / / | | | | | | | | | | | | | | | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* | / Bump versionYosys Bot2020-10-061-1/+1
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* | Update required Verific versionMiodrag Milanović2020-10-051-1/+1
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* | Bump versionYosys Bot2020-10-031-1/+1
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* | Merge pull request #2396 from YosysHQ/claire/empty-paramclairexen2020-10-021-0/+3
|\ \ | | | | | | Ignore empty parameters in Verilog module instantiations
| * | Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | | | | | | | | | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* | | Bump versionYosys Bot2020-10-021-1/+1
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* | Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-014-31/+159
|\ \ | | | | | | Added $high(), $low(), $left(), $right()
| * | We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-172-9/+20
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| * | Fixed comments, removed debug messageUdi Finkelstein2020-09-161-5/+5
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| * | Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-154-30/+147
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* | | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-0121-230/+156
|\ \ \ | | | | | | | | Clean up and parallelize testsuite
| * | | tests: add gitignores for auto-generated makefilesXiretza2020-09-262-0/+2
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| * | | tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
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| * | | tests: ParallelizeXiretza2020-09-213-9/+20
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| * | | tests: Centralize test collection and Makefile generationXiretza2020-09-2116-222/+136
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