| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | coolrunner2: Initial mapping of latches | Robert Ou | 2017-06-25 | 4 | -0/+63 | |
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| | * | coolrunner2: Initial mapping of DFFs | Robert Ou | 2017-06-25 | 4 | -0/+76 | |
| | | | | | | | | | | | All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered) | |||||
| | * | coolrunner2: Remove redundant INVERT_PTC | Robert Ou | 2017-06-25 | 2 | -4/+1 | |
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| | * | coolrunner2: Remove debug prints | Robert Ou | 2017-06-25 | 1 | -2/+0 | |
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| | * | coolrunner2: Correctly handle $_NOT_ after $sop | Robert Ou | 2017-06-25 | 1 | -5/+41 | |
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| | * | coolrunner2: Also construct the XOR cell in the macrocell | Robert Ou | 2017-06-25 | 2 | -7/+34 | |
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| | * | coolrunner2: Initial techmapping for $sop | Robert Ou | 2017-06-25 | 4 | -153/+268 | |
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| | * | coolrunner2: Initial commit | Robert Ou | 2017-06-24 | 3 | -0/+223 | |
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| * | | Merge pull request #356 from set-soft/clean-test | Clifford Wolf | 2017-07-03 | 1 | -0/+8 | |
| |\ \ | | | | | | | Added the test outputs to the clean target | |||||
| | * | | Added the test outputs to the clean target | Salvador E. Tropea | 2017-07-03 | 1 | -0/+8 | |
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| * | | | Merge pull request #355 from set-soft/exclude_TBUF_merge | Clifford Wolf | 2017-07-03 | 1 | -0/+1 | |
| |\ \ \ | |/ / |/| | | Excluded $_TBUF_ from opt_merge pass | |||||
| | * | | Excluded $_TBUF_ from opt_merge pass | Salvador E. Tropea | 2017-07-03 | 1 | -0/+1 | |
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| * | | Remove unneeded delays in smtbmc vlogtb | Clifford Wolf | 2017-07-03 | 1 | -1/+1 | |
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| * | | Include output ports with constant driver in AIGER output | Clifford Wolf | 2017-07-03 | 1 | -2/+18 | |
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| * | | Add "yosys-smtbmc --vlogtb-top" | Clifford Wolf | 2017-07-01 | 1 | -15/+32 | |
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| * | | Fix and_or_buffer optimization in opt_expr for signed operators | Clifford Wolf | 2017-07-01 | 1 | -2/+2 | |
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| * | | Fix smtbmc vlogtb bug in $anyseq handling | Clifford Wolf | 2017-07-01 | 1 | -3/+3 | |
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| * | | Add "design -import" | Clifford Wolf | 2017-06-30 | 1 | -3/+94 | |
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| * | | Add chtype command | Clifford Wolf | 2017-06-30 | 2 | -0/+84 | |
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| * | | Add $tribuf to opt_merge blacklist | Clifford Wolf | 2017-06-30 | 1 | -0/+1 | |
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| * | | Merge pull request #353 from azonenberg/master | Clifford Wolf | 2017-06-27 | 1 | -3/+21 | |
| |\ \ | | | | | | | greenpak4_counters: Use more human-readable names for inferred counters | |||||
| | * | | greenpak4_counters: Changed generation of primitive names so that the ↵ | Andrew Zonenberg | 2017-06-24 | 1 | -3/+21 | |
| |/ / | | | | | | | absorbed register's name is included | |||||
| * | | Fix handling of init values in "abc -dff" and "abc -clk" | Clifford Wolf | 2017-06-20 | 1 | -131/+176 | |
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| * | | Fix history namespace collision | Clifford Wolf | 2017-06-20 | 1 | -10/+10 | |
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| * | | Store command history when terminating with an error | Clifford Wolf | 2017-06-20 | 3 | -17/+31 | |
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| * | | Switched abc "clock domain not found" error to log_cmd_error() | Clifford Wolf | 2017-06-20 | 1 | -24/+28 | |
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| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 5 | -4/+61 | |
| | | | | | const reg" | |||||
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 | |
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| * | Update ABC to hg rev efbf7f13ea9e | Clifford Wolf | 2017-05-31 | 1 | -1/+1 | |
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| * | Add dff2ff.v techmap file | Clifford Wolf | 2017-05-31 | 2 | -0/+15 | |
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| * | Fix AIGER back-end for multiple symbols per input/latch/output/property | Clifford Wolf | 2017-05-30 | 1 | -8/+20 | |
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| * | Add "setundef -anyseq" | Clifford Wolf | 2017-05-28 | 3 | -15/+56 | |
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| * | Improve write_aiger handling of unconnected nets and constants | Clifford Wolf | 2017-05-28 | 2 | -8/+62 | |
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| * | Change default smt2 solver to yices (Yices 2 has switched its license to GPL) | Clifford Wolf | 2017-05-27 | 1 | -4/+4 | |
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| * | Add aliases for common sets of gate types to "abc -g" | Clifford Wolf | 2017-05-24 | 1 | -2/+74 | |
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| * | Add examples/osu035 | Clifford Wolf | 2017-05-23 | 4 | -0/+30 | |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-05-23 | 1 | -17/+70 | |
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| | * | Merge pull request #346 from azonenberg/master | Clifford Wolf | 2017-05-23 | 1 | -17/+70 | |
| | |\ | | | | | | | greenpak4_counters: Added support for parallel output from GP_COUNTx cells | |||||
| | | * | greenpak4_counters: Added support for parallel output from GP_COUNTx cells | Andrew Zonenberg | 2017-05-22 | 1 | -17/+70 | |
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| * / | Add workaround for CBMC bug to SimpleC back-end | Clifford Wolf | 2017-05-17 | 1 | -1/+3 | |
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| * | Enable readline and tcl in mxe builds | Clifford Wolf | 2017-05-17 | 3 | -4/+44 | |
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| * | Add missing AndnotGate() and OrnotGate() declarations to rtlil.h | Clifford Wolf | 2017-05-17 | 1 | -13/+15 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 14 | -91/+211 | |
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| * | Add <modname>_init() function generator to simpleC back-end | Clifford Wolf | 2017-05-16 | 2 | -88/+152 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-16 | 1 | -1/+1 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-15 | 1 | -42/+44 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-14 | 3 | -3/+49 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-13 | 1 | -25/+60 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-12 | 3 | -12/+78 | |
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| * | Added support for more gate types to simplec back-end | Clifford Wolf | 2017-05-12 | 1 | -1/+88 | |
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index : iCE40/yosys | |
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