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* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-111-9/+9
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* More Makefile cleanupsClifford Wolf2014-02-111-2/+3
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* Improved "make manual" and "make clean"Clifford Wolf2014-02-114-9/+13
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* Improved ilang parser error messagesClifford Wolf2014-02-091-9/+9
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* fixed a bug in subcircuit library with cells that have connections to itselfClifford Wolf2014-02-091-1/+4
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* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-091-36/+119
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* Added delete {-input|-output|-port}Clifford Wolf2014-02-091-5/+36
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* Bugfix in delete commandClifford Wolf2014-02-091-1/+3
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* Added test cases for expose -evert-dffClifford Wolf2014-02-082-0/+48
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* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-081-0/+1
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* Build fixes for log cmdClifford Wolf2014-02-081-2/+2
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-082-0/+79
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| * Merge pull request #24 from hansiglaser/masterClifford Wolf2014-02-082-0/+79
| |\ | | | | | | added "log" command
| | * added "log" commandJohann Glaser2014-02-082-0/+79
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* | Implemented expose -evert-dffClifford Wolf2014-02-081-11/+301
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* | Improved checking of internal cell conventionsClifford Wolf2014-02-081-8/+17
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* | Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-081-0/+1
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* Added various new options to splice commandClifford Wolf2014-02-081-5/+105
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* Added %a select operatorClifford Wolf2014-02-081-0/+32
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* Moved some passes to other source directoriesClifford Wolf2014-02-089-9/+3
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* Added support for "keep" attribute to abc passClifford Wolf2014-02-081-1/+1
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* Added opt -purge (frontend to opt_clean -purge)Clifford Wolf2014-02-081-3/+8
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* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-081-2/+13
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* Added checking for ABC modifications to Makefile and made sure we do not ↵Clifford Wolf2014-02-081-1/+4
| | | | have the word ERROR in regular make output
* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-081-3/+10
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* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-071-4/+23
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* Added splice commandClifford Wolf2014-02-074-0/+281
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* Added log_header() to splitnetsClifford Wolf2014-02-071-0/+2
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* Added $slice and $concat to CellTypes listClifford Wolf2014-02-071-0/+2
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* Added $slice and $concat cell typesClifford Wolf2014-02-078-4/+140
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* Stronger checking of internal cellsClifford Wolf2014-02-071-29/+37
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* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-071-7/+0
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* Added echo commandClifford Wolf2014-02-073-4/+47
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* Fixed use of "cmd_error" in passes/cmds/design.ccClifford Wolf2014-02-071-2/+2
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-062-2/+2
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* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim ↵Clifford Wolf2014-02-061-0/+7
| | | | failed)
* Updated ABC to rev 10cc13a2a0f1Clifford Wolf2014-02-061-1/+1
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* Added "retime" to standard ABC recipesClifford Wolf2014-02-061-4/+4
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* Added copy commandClifford Wolf2014-02-062-0/+55
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* Added design -stash/-copy-from/-copy-toClifford Wolf2014-02-061-13/+99
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* Added support for s: select expressions (wire width)Clifford Wolf2014-02-061-1/+21
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* Added i:, o:, and x: selection patternClifford Wolf2014-02-061-0/+18
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* Added support for %m selection opClifford Wolf2014-02-061-0/+16
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-061-0/+25
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| * Merge pull request #23 from hansiglaser/masterClifford Wolf2014-02-061-0/+25
| |\ | | | | | | new %s: add sub-modules to selection
| | * new %s: add sub-modules to selectionJohann Glaser2014-02-061-0/+25
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* / Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-065-37/+39
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* Added support for sat -show @<sel_name>Clifford Wolf2014-02-061-0/+17
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* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-061-4/+34
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* Added opt_const -undrivenClifford Wolf2014-02-062-3/+68
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