3 files changed, 9 insertions, 4 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 58596d701..65eb01338 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -268,13 +268,18 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk, d, r, output reg q);
+module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+always @(posedge clk1) q1 <= d;
+always @(negedge clk2) q2 <= q1;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
 always @(posedge clk or posedge r)
     if (r) q <= 1'b0;
     else q <= d;
 endmodule
 
-module abc9_test030(input clk, d, r, output reg q);
+module abc9_test031(input clk, d, r, output reg q);
 always @(negedge clk or posedge r)
     if (r) q <= 1'b1;
     else q <= d;
diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index e53dcdb21..85828bf30 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -10,7 +10,7 @@ unknown u(~i, w);
 unknown2 u2(w, o);
 endmodule
 
-module abc9_test031(input clk, d, r, output reg q);
+module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)
     if (r) q <= 1'b0;
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index f7a3f1fa0..81d0afd1b 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -24,7 +24,7 @@ select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
 
 design -load read
-hierarchy -top abc9_test031
+hierarchy -top abc9_test032
 proc
 clk2fflogic
 design -save gold