diff options
Diffstat (limited to 'tests')
23 files changed, 1324 insertions, 9 deletions
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index e1f748e26..f55bf01d2 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom -write_ilang synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:PDPW16KD # too inefficient select -assert-min 18 t:LUT4 @@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom -write_ilang synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # too inefficient select -assert-min 9 t:LUT4 diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 571edec1d..c32f12315 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom -write_ilang synth_ice40 -top sync_rom; cd sync_rom select -assert-count 0 t:SB_RAM40_4K # too inefficient select -assert-min 1 t:SB_LUT4 diff --git a/tests/select/unset.ys b/tests/select/unset.ys new file mode 100644 index 000000000..4f60781c2 --- /dev/null +++ b/tests/select/unset.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module top(input i, output o); +assign o = i; +endmodule +EOT +select -set foo w:* +select -assert-any @foo +select -unset foo +logger -expect error "Selection '\\foo' does not exist!" 1 +select -unset foo diff --git a/tests/select/unset2.ys b/tests/select/unset2.ys new file mode 100644 index 000000000..456b84c22 --- /dev/null +++ b/tests/select/unset2.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module top(input i, output o); +assign o = i; +endmodule +EOT +select -set foo w:* +select -assert-any @foo +select -unset foo +logger -expect error "Selection @foo is not defined!" 1 +select -list @foo diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 0c7695089..6e2415ad7 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -53,3 +53,22 @@ assign q = w; endmodule EOT abc9 -lut 4 -dff + + +design -reset +read_verilog -icells -specify <<EOT +(* abc9_lut=1, blackbox *) +module LUT2(input [1:0] i, output o); +parameter [3:0] mask = 0; +assign o = i[0] ? (i[1] ? mask[3] : mask[2]) + : (i[1] ? mask[1] : mask[0]); +specify + (i *> o) = 1; +endspecify +endmodule + +module top(input [1:0] i, output o); +LUT2 #(.mask(4'b0)) lut (.i(i), .o(o)); +endmodule +EOT +abc9 diff --git a/tests/various/design.ys b/tests/various/design.ys index f13ad8171..a64430dc7 100644 --- a/tests/various/design.ys +++ b/tests/various/design.ys @@ -1,9 +1,17 @@ read_verilog <<EOT +(* blackbox *) +module bb(input i, output o); +endmodule + +(* whitebox *) +module wb(input i, output o); +assign o = ~i; +endmodule + module top(input i, output o); -assign o = i; +assign o = ~i; endmodule EOT -design -stash foo -design -delete foo -logger -expect error "No saved design 'foo' found!" 1 -design -delete foo + +design -stash gate +design -import gate -as gate diff --git a/tests/various/design1.ys b/tests/various/design1.ys new file mode 100644 index 000000000..f13ad8171 --- /dev/null +++ b/tests/various/design1.ys @@ -0,0 +1,9 @@ +read_verilog <<EOT +module top(input i, output o); +assign o = i; +endmodule +EOT +design -stash foo +design -delete foo +logger -expect error "No saved design 'foo' found!" 1 +design -delete foo diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys new file mode 100644 index 000000000..abc1daad6 --- /dev/null +++ b/tests/various/dynamic_part_select.ys @@ -0,0 +1,106 @@ +### Original testcase ### +read_verilog ./dynamic_part_select/original.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/original_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +### Multiple blocking assingments ### +design -reset +read_verilog ./dynamic_part_select/multiple_blocking.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/multiple_blocking_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +### Non-blocking to the same output register ### +design -reset +read_verilog ./dynamic_part_select/nonblocking.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/nonblocking_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +### For-loop select, one dynamic input +design -reset +read_verilog ./dynamic_part_select/forloop_select.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/forloop_select_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +#### Double loop (part-select, reset) ### +design -reset +read_verilog ./dynamic_part_select/reset_test.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/reset_test_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +### Reversed part-select case ### +design -reset +read_verilog ./dynamic_part_select/reversed.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/reversed_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv diff --git a/tests/various/dynamic_part_select/forloop_select.v b/tests/various/dynamic_part_select/forloop_select.v new file mode 100644 index 000000000..8260f3186 --- /dev/null +++ b/tests/various/dynamic_part_select/forloop_select.v @@ -0,0 +1,19 @@ +module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input en, + output reg [WIDTH-1:0] dout); + + reg [SELW:0] sel; + localparam SLICE = WIDTH/(SELW**2); + + always @(posedge clk) + begin + if (en) begin + for (sel = 0; sel <= 4'hf; sel=sel+1'b1) + dout[(ctrl*sel)+:SLICE] <= din; + end + end +endmodule + diff --git a/tests/various/dynamic_part_select/forloop_select_gate.v b/tests/various/dynamic_part_select/forloop_select_gate.v new file mode 100644 index 000000000..71ae88537 --- /dev/null +++ b/tests/various/dynamic_part_select/forloop_select_gate.v @@ -0,0 +1,559 @@ +module forloop_select_gate (clk, ctrl, din, en, dout); + input clk; + input [3:0] ctrl; + input [15:0] din; + input en; + output reg [15:0] dout; + reg [4:0] sel; + always @(posedge clk) + case (|(en)) + 1'b 1: + begin + case (({(ctrl)*(0)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00001)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00010)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00011)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00100)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00101)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00110)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00111)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01000)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01001)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01010)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01011)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01100)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01101)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01110)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01111)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + sel = 5'b 10000; + end + endcase + endmodule diff --git a/tests/various/dynamic_part_select/multiple_blocking.v b/tests/various/dynamic_part_select/multiple_blocking.v new file mode 100644 index 000000000..2858f7741 --- /dev/null +++ b/tests/various/dynamic_part_select/multiple_blocking.v @@ -0,0 +1,19 @@ +module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + reg [CTRLW:0] a; + reg [SELW-1:0] b; + reg [DINW:0] c; + always @(posedge clk) begin + a = ctrl + 1; + b = sel - 1; + c = ~din; + dout = dout + 1; + dout[a*b+:SLICE] = c; + end +endmodule diff --git a/tests/various/dynamic_part_select/multiple_blocking_gate.v b/tests/various/dynamic_part_select/multiple_blocking_gate.v new file mode 100644 index 000000000..073b559dc --- /dev/null +++ b/tests/various/dynamic_part_select/multiple_blocking_gate.v @@ -0,0 +1,83 @@ +module multiple_blocking_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + reg [5:0] a; + reg [0:0] b; + reg [2:0] c; + always @(posedge clk) + begin + a = (ctrl)+(1); + b = (sel)-(1); + c = ~(din); + dout = (dout)+(1); + case (({(a)*(b)})+(0)) + 0: + dout[31:0] = c; + 1: + dout[31:1] = c; + 2: + dout[31:2] = c; + 3: + dout[31:3] = c; + 4: + dout[31:4] = c; + 5: + dout[31:5] = c; + 6: + dout[31:6] = c; + 7: + dout[31:7] = c; + 8: + dout[31:8] = c; + 9: + dout[31:9] = c; + 10: + dout[31:10] = c; + 11: + dout[31:11] = c; + 12: + dout[31:12] = c; + 13: + dout[31:13] = c; + 14: + dout[31:14] = c; + 15: + dout[31:15] = c; + 16: + dout[31:16] = c; + 17: + dout[31:17] = c; + 18: + dout[31:18] = c; + 19: + dout[31:19] = c; + 20: + dout[31:20] = c; + 21: + dout[31:21] = c; + 22: + dout[31:22] = c; + 23: + dout[31:23] = c; + 24: + dout[31:24] = c; + 25: + dout[31:25] = c; + 26: + dout[31:26] = c; + 27: + dout[31:27] = c; + 28: + dout[31:28] = c; + 29: + dout[31:29] = c; + 30: + dout[31:30] = c; + 31: + dout[31:31] = c; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/nonblocking.v b/tests/various/dynamic_part_select/nonblocking.v new file mode 100644 index 000000000..0949b31a9 --- /dev/null +++ b/tests/various/dynamic_part_select/nonblocking.v @@ -0,0 +1,14 @@ +module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout <= dout + 1; + dout[ctrl*sel+:SLICE] <= din ; + end + +endmodule diff --git a/tests/various/dynamic_part_select/nonblocking_gate.v b/tests/various/dynamic_part_select/nonblocking_gate.v new file mode 100644 index 000000000..ed1ee2776 --- /dev/null +++ b/tests/various/dynamic_part_select/nonblocking_gate.v @@ -0,0 +1,77 @@ +module nonblocking_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + always @(posedge clk) + begin + dout <= (dout)+(1); + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/original.v b/tests/various/dynamic_part_select/original.v new file mode 100644 index 000000000..f7dfed1a1 --- /dev/null +++ b/tests/various/dynamic_part_select/original.v @@ -0,0 +1,12 @@ +module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) + begin + dout[ctrl*sel+:SLICE] <= din ; + end +endmodule diff --git a/tests/various/dynamic_part_select/original_gate.v b/tests/various/dynamic_part_select/original_gate.v new file mode 100644 index 000000000..22093bf63 --- /dev/null +++ b/tests/various/dynamic_part_select/original_gate.v @@ -0,0 +1,74 @@ +module original_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + always @(posedge clk) + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase +endmodule diff --git a/tests/various/dynamic_part_select/reset_test.v b/tests/various/dynamic_part_select/reset_test.v new file mode 100644 index 000000000..29355aafb --- /dev/null +++ b/tests/various/dynamic_part_select/reset_test.v @@ -0,0 +1,23 @@ +module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + reg [SELW:0] i; + wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}}; + localparam SLICE = WIDTH/(SELW**2); + // Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for + // whatever reason. + always @(posedge clk) begin + if (reset) begin: reset_mask + for (i = 0; i < {SELW{1'b1}}; i=i+1) begin + dout[i*rval+:SLICE] <= 32'hDEAD; + end + end + //else begin + dout[ctrl*sel+:SLICE] <= din; + //end + end +endmodule diff --git a/tests/various/dynamic_part_select/reset_test_gate.v b/tests/various/dynamic_part_select/reset_test_gate.v new file mode 100644 index 000000000..96dff4135 --- /dev/null +++ b/tests/various/dynamic_part_select/reset_test_gate.v @@ -0,0 +1,151 @@ +module reset_test_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + reg [1:0] i; + wire [0:0] rval; + assign rval = {reset, 1'b0 }; + always @(posedge clk) + begin + case (|(reset)) + 1'b 1: + begin + case (({(0)*(rval)})+(0)) + 0: + dout[31:0] <= 57005; + 1: + dout[31:1] <= 57005; + 2: + dout[31:2] <= 57005; + 3: + dout[31:3] <= 57005; + 4: + dout[31:4] <= 57005; + 5: + dout[31:5] <= 57005; + 6: + dout[31:6] <= 57005; + 7: + dout[31:7] <= 57005; + 8: + dout[31:8] <= 57005; + 9: + dout[31:9] <= 57005; + 10: + dout[31:10] <= 57005; + 11: + dout[31:11] <= 57005; + 12: + dout[31:12] <= 57005; + 13: + dout[31:13] <= 57005; + 14: + dout[31:14] <= 57005; + 15: + dout[31:15] <= 57005; + 16: + dout[31:16] <= 57005; + 17: + dout[31:17] <= 57005; + 18: + dout[31:18] <= 57005; + 19: + dout[31:19] <= 57005; + 20: + dout[31:20] <= 57005; + 21: + dout[31:21] <= 57005; + 22: + dout[31:22] <= 57005; + 23: + dout[31:23] <= 57005; + 24: + dout[31:24] <= 57005; + 25: + dout[31:25] <= 57005; + 26: + dout[31:26] <= 57005; + 27: + dout[31:27] <= 57005; + 28: + dout[31:28] <= 57005; + 29: + dout[31:29] <= 57005; + 30: + dout[31:30] <= 57005; + 31: + dout[31:31] <= 57005; + endcase + i = 1; + end + endcase + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/reversed.v b/tests/various/dynamic_part_select/reversed.v new file mode 100644 index 000000000..8b114ac77 --- /dev/null +++ b/tests/various/dynamic_part_select/reversed.v @@ -0,0 +1,13 @@ +module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout[(WIDTH-ctrl*sel)-:SLICE] <= din; + end +endmodule + diff --git a/tests/various/dynamic_part_select/reversed_gate.v b/tests/various/dynamic_part_select/reversed_gate.v new file mode 100644 index 000000000..9349d45ee --- /dev/null +++ b/tests/various/dynamic_part_select/reversed_gate.v @@ -0,0 +1,74 @@ +module reversed_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [15:0] din; + input [3:0] sel; + output reg [31:0] dout; + always @(posedge clk) + case ((({(32)-((ctrl)*(sel))})+(1))-(2)) + 0: + dout[1:0] <= din; + 1: + dout[2:1] <= din; + 2: + dout[3:2] <= din; + 3: + dout[4:3] <= din; + 4: + dout[5:4] <= din; + 5: + dout[6:5] <= din; + 6: + dout[7:6] <= din; + 7: + dout[8:7] <= din; + 8: + dout[9:8] <= din; + 9: + dout[10:9] <= din; + 10: + dout[11:10] <= din; + 11: + dout[12:11] <= din; + 12: + dout[13:12] <= din; + 13: + dout[14:13] <= din; + 14: + dout[15:14] <= din; + 15: + dout[16:15] <= din; + 16: + dout[17:16] <= din; + 17: + dout[18:17] <= din; + 18: + dout[19:18] <= din; + 19: + dout[20:19] <= din; + 20: + dout[21:20] <= din; + 21: + dout[22:21] <= din; + 22: + dout[23:22] <= din; + 23: + dout[24:23] <= din; + 24: + dout[25:24] <= din; + 25: + dout[26:25] <= din; + 26: + dout[27:26] <= din; + 27: + dout[28:27] <= din; + 28: + dout[29:28] <= din; + 29: + dout[30:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase +endmodule diff --git a/tests/various/hierarchy_param.ys b/tests/various/hierarchy_param.ys new file mode 100644 index 000000000..d703bb713 --- /dev/null +++ b/tests/various/hierarchy_param.ys @@ -0,0 +1,23 @@ +read_verilog <<EOT + +module bb (...); +parameter A = "abc"; +parameter B = 1; +parameter C = 2; +input a; +output b; +endmodule + +module top (...); +input a; +output b; +bb #("def", 3) my_bb (a, b); +endmodule + +EOT + +hierarchy -top top +dump + +select -assert-count 1 t:bb r:A=def %i +select -assert-count 1 t:bb r:B=3 %i diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh index d6d4aee59..2880c8c06 100644 --- a/tests/various/plugin.sh +++ b/tests/various/plugin.sh @@ -1,6 +1,8 @@ set -e rm -f plugin.so CXXFLAGS=$(../../yosys-config --cxxflags) -CXXFLAGS=${CXXFLAGS// -I\/usr\/local\/share\/yosys\/include/ -I..\/..\/share\/include} +DATDIR=$(../../yosys-config --datdir) +DATDIR=${DATDIR//\//\\\/} +CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} ../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc ../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!" diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys new file mode 100644 index 000000000..d778b92cd --- /dev/null +++ b/tests/various/sim_const.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module top(input clk, output reg [1:0] q); + wire [1:0] x = 2'b10; + always @(posedge clk) + q <= x & 2'b11; +endmodule +EOT + +proc +sim -clock clk -n 1 -w top +select -assert-count 1 a:init=2'b10 top/q %i + |