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-rw-r--r--tests/simple/matching_end_labels.sv29
-rw-r--r--tests/verilog/block_end_label_only.ys9
-rw-r--r--tests/verilog/block_end_label_wrong.ys9
-rw-r--r--tests/verilog/gen_block_end_label_only.ys9
-rw-r--r--tests/verilog/gen_block_end_label_wrong.ys9
-rw-r--r--tests/verilog/module_end_label.ys15
6 files changed, 80 insertions, 0 deletions
diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv
new file mode 100644
index 000000000..09182ebcf
--- /dev/null
+++ b/tests/simple/matching_end_labels.sv
@@ -0,0 +1,29 @@
+module top(
+ output reg [7:0]
+ out1, out2, out3, out4
+);
+ initial begin
+ begin : blk1
+ reg x;
+ x = 1;
+ end
+ out1 = blk1.x;
+ begin : blk2
+ reg x;
+ x = 2;
+ end : blk2
+ out2 = blk2.x;
+ end
+ if (1) begin
+ if (1) begin : blk3
+ reg x;
+ assign x = 3;
+ end
+ assign out3 = blk3.x;
+ if (1) begin : blk4
+ reg x;
+ assign x = 4;
+ end : blk4
+ assign out4 = blk4.x;
+ end
+endmodule
diff --git a/tests/verilog/block_end_label_only.ys b/tests/verilog/block_end_label_only.ys
new file mode 100644
index 000000000..5db1c7879
--- /dev/null
+++ b/tests/verilog/block_end_label_only.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+read_verilog -sv <<EOF
+module top;
+initial
+ begin
+ $display("HI");
+ end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/block_end_label_wrong.ys b/tests/verilog/block_end_label_wrong.ys
new file mode 100644
index 000000000..47dbbe32f
--- /dev/null
+++ b/tests/verilog/block_end_label_wrong.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module top;
+initial
+ begin : correct_name
+ $display("HI");
+ end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/gen_block_end_label_only.ys b/tests/verilog/gen_block_end_label_only.ys
new file mode 100644
index 000000000..60dc0476a
--- /dev/null
+++ b/tests/verilog/gen_block_end_label_only.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+read_verilog -sv <<EOF
+module top;
+if (1)
+ begin
+ initial $display("HI");
+ end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/gen_block_end_label_wrong.ys b/tests/verilog/gen_block_end_label_wrong.ys
new file mode 100644
index 000000000..43cfc8773
--- /dev/null
+++ b/tests/verilog/gen_block_end_label_wrong.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module top;
+if (1)
+ begin : correct_name
+ initial $display("HI");
+ end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/module_end_label.ys b/tests/verilog/module_end_label.ys
new file mode 100644
index 000000000..c9e5a13a2
--- /dev/null
+++ b/tests/verilog/module_end_label.ys
@@ -0,0 +1,15 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module correct_name;
+localparam X = 1;
+endmodule : correct_name
+EOF
+
+design -reset
+
+logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module correct_name;
+localparam X = 1;
+endmodule : incorrect_name
+EOF