2 files changed, 66 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
new file mode 100644
index 000000000..6f997b67b
--- /dev/null
+++ b/tests/arch/intel_alm/lutram.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 16 t:MISTRAL_MLAB
+select -assert-count 1 t:MISTRAL_NOT
+select -assert-count 2 t:MISTRAL_ALUT2
+select -assert-count 8 t:MISTRAL_ALUT3
+select -assert-count 17 t:MISTRAL_FF
+select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 83493fcb0..5e9730d6b 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -64,3 +64,49 @@ endmodule
 module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
 assign dout = din[a*b +: 2];
 endmodule
+
+module partsel_test004 (
+	input [31:0] din,
+	input signed [4:0] n,
+	output reg [31:0] dout
+);
+	always @(*) begin
+		dout = 0;
+		dout[n+1 +: 2] = din[n +: 2];
+	end
+endmodule
+
+
+module partsel_test005 (
+	input [31:0] din,
+	input signed [4:0] n,
+	output reg [31:0] dout
+);
+	always @(*) begin
+		dout = 0;
+		dout[n+1] = din[n];
+	end
+endmodule
+
+module partsel_test006 (
+	input [31:-32] din,
+	input signed [4:0] n,
+	output reg [31:-32] dout
+);
+	always @(*) begin
+		dout = 0;
+		dout[n+1 +: 2] = din[n +: 2];
+	end
+endmodule
+
+
+module partsel_test007 (
+	input [31:-32] din,
+	input signed [4:0] n,
+	output reg [31:-32] dout
+);
+	always @(*) begin
+		dout = 0;
+		dout[n+1] = din[n];
+	end
+endmodule