diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/tribuf.sh | 4 | ||||
| -rw-r--r-- | tests/bram/run-single.sh | 2 | ||||
| -rwxr-xr-x | tests/memories/run-test.sh | 2 | ||||
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 | ||||
| -rw-r--r-- | tests/techmap/recursive_runtest.sh | 2 | ||||
| -rw-r--r-- | tests/various/async.sh | 8 |
6 files changed, 10 insertions, 10 deletions
diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh index bd44395cb..eca33e490 100644 --- a/tests/arch/xilinx/tribuf.sh +++ b/tests/arch/xilinx/tribuf.sh @@ -1,5 +1,5 @@ -! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v -../../../yosys -qp "synth_xilinx -iopad; \ +../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v +../../../yosys -f verilog -qp "synth_xilinx -iopad; \ select -assert-count 2 t:IBUF; \ select -assert-count 1 t:INV; \ select -assert-count 1 t:OBUFT" ../common/tribuf.v diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 98a45b613..429a79e3c 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index b8657056a..c65066a9c 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -18,7 +18,7 @@ ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do echo -n "Testing expectations for $f .." - ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f + ../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f if grep -q expect-wr-ports $f; then grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected number of write ports."; false; } diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 9c41fa56a..b486de5c7 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -e -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 0725ccf40..564d678fa 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ set -e -../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v +../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' diff --git a/tests/various/async.sh b/tests/various/async.sh index 7c41d6d94..e83935d02 100644 --- a/tests/various/async.sh +++ b/tests/various/async.sh @@ -1,9 +1,9 @@ #!/bin/bash set -ex -../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v -../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v -../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v -../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v +../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v +../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v +../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v +../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v iverilog -o async_sim -DTESTBENCH async.v async_???.v vvp -N async_sim > async.out tail async.out |