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-rw-r--r--tests/select/no_warn_assert.ys2
-rw-r--r--tests/select/no_warn_prefixed_arg_memb.ys5
-rw-r--r--tests/select/no_warn_prefixed_empty_select_arg.ys3
-rwxr-xr-xtests/select/run-test.sh6
-rw-r--r--tests/select/warn_empty_select_arg.ys3
-rw-r--r--tests/techmap/techmap_replace.ys18
-rw-r--r--tests/various/sv_defines.ys33
-rw-r--r--tests/various/sv_defines_dup.ys5
-rw-r--r--tests/various/sv_defines_mismatch.ys5
-rw-r--r--tests/various/sv_defines_too_few.ys7
10 files changed, 87 insertions, 0 deletions
diff --git a/tests/select/no_warn_assert.ys b/tests/select/no_warn_assert.ys
new file mode 100644
index 000000000..889315826
--- /dev/null
+++ b/tests/select/no_warn_assert.ys
@@ -0,0 +1,2 @@
+logger -expect-no-warnings
+select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
diff --git a/tests/select/no_warn_prefixed_arg_memb.ys b/tests/select/no_warn_prefixed_arg_memb.ys
new file mode 100644
index 000000000..596a6ed70
--- /dev/null
+++ b/tests/select/no_warn_prefixed_arg_memb.ys
@@ -0,0 +1,5 @@
+logger -expect-no-warnings
+read_verilog ../../examples/igloo2/example.v
+hierarchy
+proc
+select example/t:$add
diff --git a/tests/select/no_warn_prefixed_empty_select_arg.ys b/tests/select/no_warn_prefixed_empty_select_arg.ys
new file mode 100644
index 000000000..617e0d63e
--- /dev/null
+++ b/tests/select/no_warn_prefixed_empty_select_arg.ys
@@ -0,0 +1,3 @@
+logger -expect-no-warnings
+select n:foo/bar*
+select t:$assert
diff --git a/tests/select/run-test.sh b/tests/select/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/select/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+ echo "Running $x.."
+ ../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/select/warn_empty_select_arg.ys b/tests/select/warn_empty_select_arg.ys
new file mode 100644
index 000000000..55aca8eb6
--- /dev/null
+++ b/tests/select/warn_empty_select_arg.ys
@@ -0,0 +1,3 @@
+logger -expect warning "did not match any module." 1
+logger -expect warning "did not match any object." 1
+select foo/bar
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
techmap -map %techmap
select -assert-any w:s0.asdf
select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah
diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys
new file mode 100644
index 000000000..8e70ee0ee
--- /dev/null
+++ b/tests/various/sv_defines.ys
@@ -0,0 +1,33 @@
+# Check that basic macro expansions do what you'd expect
+
+read_verilog <<EOT
+`define empty_arglist() 123
+`define one_arg(x) 123+x
+`define opt_arg(x = 1) 123+x
+`define two_args(x, y = (1+23)) x+y
+`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y
+
+module top;
+ localparam a = `empty_arglist();
+ localparam b = `one_arg(10);
+ localparam c = `opt_arg(10);
+ localparam d = `opt_arg();
+ localparam e = `two_args(1,2);
+ localparam f = `two_args(1);
+ localparam g = `nested_comma(1, 2);
+ localparam h = `nested_comma({31'b0, (1'b0)});
+ localparam i = `nested_comma(, 1);
+
+ generate
+ if (a != 123) $error("a bad");
+ if (b != 133) $error("b bad");
+ if (c != 133) $error("c bad");
+ if (d != 124) $error("d bad");
+ if (e != 3) $error("e bad");
+ if (f != 25) $error("f bad");
+ if (g != 3) $error("g bad");
+ if (h != 3) $error("h bad");
+ if (i != 2) $error("i bad");
+ endgenerate
+endmodule
+EOT
diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys
new file mode 100644
index 000000000..38418ba8f
--- /dev/null
+++ b/tests/various/sv_defines_dup.ys
@@ -0,0 +1,5 @@
+# Check for duplicate arguments
+logger -expect error "Duplicate macro arguments with name `x'" 1
+read_verilog <<EOT
+`define duplicate_arg(x, x)
+EOT
diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys
new file mode 100644
index 000000000..ab6e899de
--- /dev/null
+++ b/tests/various/sv_defines_mismatch.ys
@@ -0,0 +1,5 @@
+# Check that we spot mismatched brackets
+logger -expect error "Mismatched brackets in macro argument: \[ and }." 1
+read_verilog <<EOT
+`define foo(x=[1,2})
+EOT
diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys
new file mode 100644
index 000000000..295884809
--- /dev/null
+++ b/tests/various/sv_defines_too_few.ys
@@ -0,0 +1,7 @@
+# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
+# arguments actually passes 1 empty argument).
+logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
+read_verilog <<EOT
+`define foo(x=1, y)
+`foo()
+EOT