diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/nexus/mul.ys | 46 | ||||
| -rw-r--r-- | tests/arch/nexus/run-test.sh | 22 |
2 files changed, 37 insertions, 31 deletions
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys index 27ea3e04e..65a2fd8c3 100644 --- a/tests/arch/nexus/mul.ys +++ b/tests/arch/nexus/mul.ys @@ -1,4 +1,5 @@ read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc @@ -7,22 +8,43 @@ design -save read equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:CCU2 -select -assert-max 5 t:WIDEFN9 -select -assert-max 62 t:LUT4 +select -assert-count 1 t:MULT9X9 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D -design -load read -equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X36 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D -stat -select -assert-count 7 t:CCU2 -select -assert-max 12 t:WIDEFN9 -select -assert-max 58 t:LUT4 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D diff --git a/tests/arch/nexus/run-test.sh b/tests/arch/nexus/run-test.sh index bf19b887d..4be4b70ae 100644 --- a/tests/arch/nexus/run-test.sh +++ b/tests/arch/nexus/run-test.sh @@ -1,20 +1,4 @@ #!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk +set -eu +source ../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" |