diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ecp5/mux.ys | 6 | ||||
| -rw-r--r-- | tests/arch/efinix/mux.ys | 4 | ||||
| -rw-r--r-- | tests/techmap/shiftx2mux.ys | 110 |
3 files changed, 115 insertions, 5 deletions
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 22866832d..92463aa32 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:L6MUX21 -select -assert-count 34 t:LUT4 -select -assert-count 17 t:PFUMX +select -assert-count 8 t:L6MUX21 +select -assert-count 26 t:LUT4 +select -assert-count 12 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index a5ab80d8b..67006b6f2 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -16,7 +16,7 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 +#select -assert-count 2 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D @@ -26,7 +26,7 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:EFX_LUT4 +#select -assert-count 5 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys new file mode 100644 index 000000000..c13b5f600 --- /dev/null +++ b/tests/techmap/shiftx2mux.ys @@ -0,0 +1,110 @@ +read_verilog <<EOT +module sc1 (i1 , + i2 , + i3 , + i4 , + i5 , + i6 , + i7 , + i8 , + i9 , + i10, + i11, + i12, + i13, + i14, + i15, + binary_out, + encoder_in, + enable +); + +input [3:0] i1 ; +input [3:0] i2 ; +input [3:0] i3 ; +input [3:0] i4 ; +input [3:0] i5 ; +input [3:0] i6 ; +input [3:0] i7 ; +input [3:0] i8 ; +input [3:0] i9 ; +input [3:0] i10 ; +input [3:0] i11 ; +input [3:0] i12 ; +input [3:0] i13 ; +input [3:0] i14 ; +input [3:0] i15 ; + +output reg [3:0] binary_out ; + +input [3:0] encoder_in ; +input enable ; + + + +always @ (*) +begin + binary_out = 0; + if (enable) begin + case (encoder_in) + 4'h1 : binary_out = i1; + 4'h2 : binary_out = i2; + 4'h3 : binary_out = i3; + 4'h4 : binary_out = i4; + 4'h5 : binary_out = i5; + 4'h6 : binary_out = i6; + 4'h7 : binary_out = i7; + 4'h8 : binary_out = i8; + 4'h9 : binary_out = i9; + 4'ha : binary_out = i10; + 4'hb : binary_out = i11;/* + 4'hc : binary_out = i12; + 4'hd : binary_out = i13; + 4'he : binary_out = i14; + 4'hf : binary_out = i15;*/ + endcase + end +end +endmodule +EOT + +proc +pmux2shiftx +design -save gold + + +design -load gold +techmap -D NO_LSB_FIRST_SHIFT_SHIFTX +abc -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap +abc -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -load gold +techmap -D NO_LSB_FIRST_SHIFT_SHIFTX +abc9 -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap +abc9 -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + |