diff options
Diffstat (limited to 'tests')
-rw-r--r-- | tests/arch/gowin/mux.ys | 1 | ||||
-rw-r--r-- | tests/simple_abc9/abc9.v | 12 | ||||
-rw-r--r-- | tests/various/submod.ys | 50 | ||||
-rwxr-xr-x | tests/various/svalways.sh | 63 |
4 files changed, 124 insertions, 2 deletions
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index 4990be421..afad29a89 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -45,6 +45,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux16 # Constrain all select calls below inside the top module select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF -show select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 65eb01338..99075d319 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -268,7 +268,7 @@ assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule -module abc9_test029(input clk1, clk2, input d, output reg q1, q2); +module abc9_test029(input clk1, clk2, d, output reg q1, q2); always @(posedge clk1) q1 <= d; always @(negedge clk2) q2 <= q1; endmodule @@ -284,3 +284,13 @@ always @(negedge clk or posedge r) if (r) q <= 1'b1; else q <= d; endmodule + +module abc9_test033(input clk, d, output reg q1, q2); +always @(posedge clk) q1 <= d; +always @(posedge clk) q2 <= q1; +endmodule + +module abc9_test034(input clk, d, output reg [1:0] q); +always @(posedge clk) q[0] <= d; +always @(negedge clk) q[1] <= q[0]; +endmodule diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..7c6f555ac --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,50 @@ +read_verilog <<EOT +module top(input a, output [1:0] b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b[0] = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b); +(* submod="bar" *) sub s1(a, b[1]); +assign b[0] = 1'b0; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter diff --git a/tests/various/svalways.sh b/tests/various/svalways.sh new file mode 100755 index 000000000..2cc09f801 --- /dev/null +++ b/tests/various/svalways.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR + +# Good case +../../yosys -f "verilog -sv" -qp proc - <<EOT +module top(input clk, en, d, output reg p, q, r); + +always_ff @(posedge clk) + p <= d; + +always_comb + q = ~d; + +always_latch + if (en) r = d; + +endmodule +EOT + +# Incorrect always_comb syntax +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input d, output reg q); + +always_comb @(d) + q = ~d; + +endmodule +EOT +) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null + +# Incorrect use of always_comb +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_comb + if (en) q = d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null + +# Incorrect use of always_latch +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_latch + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null + +# Incorrect use of always_ff +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_ff @(*) + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Found non edge/level sensitive event in always_ff process" > /dev/null |