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-rw-r--r--tests/arch/ice40/bug1626.ys217
1 files changed, 217 insertions, 0 deletions
diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys
new file mode 100644
index 000000000..27b6fb5e8
--- /dev/null
+++ b/tests/arch/ice40/bug1626.ys
@@ -0,0 +1,217 @@
+read_ilang <<EOT
+# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
+autoidx 2815
+attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"
+attribute \cells_not_processed 1
+attribute \dynports 1
+module \ahb_async_sram_halfwidth
+ parameter \DEPTH
+ parameter \W_ADDR
+ parameter \W_BYTEADDR
+ parameter \W_DATA
+ parameter \W_SRAM_ADDR
+ parameter \W_SRAM_DATA
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire $0\addr_lsb[0:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire $0\hready_r[0:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire $0\long_dphase[0:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire width 16 $0\rdata_buf[15:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire $0\read_dph[0:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ wire $0\write_dph[0:0]
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+ wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
+ wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+ wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+ wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+ wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+ wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
+ wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+ wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
+ wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
+ wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+ wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+ wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+ wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+ wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
+ wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+ wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+ wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65"
+ wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50"
+ wire \addr_lsb
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24"
+ wire width 32 \ahbls_haddr
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28"
+ wire width 3 \ahbls_hburst
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30"
+ wire \ahbls_hmastlock
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29"
+ wire width 4 \ahbls_hprot
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32"
+ wire width 32 \ahbls_hrdata
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22"
+ wire \ahbls_hready
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21"
+ wire \ahbls_hready_resp
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23"
+ wire \ahbls_hresp
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27"
+ wire width 3 \ahbls_hsize
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26"
+ wire width 2 \ahbls_htrans
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31"
+ wire width 32 \ahbls_hwdata
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25"
+ wire \ahbls_hwrite
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+ wire \aphase_full_width
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
+ wire width 2 \bytemask
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+ wire width 2 \bytemask_noshift
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17"
+ wire \clk
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46"
+ wire \hready_r
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47"
+ wire \long_dphase
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64"
+ wire width 16 \rdata_buf
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49"
+ wire \read_dph
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18"
+ wire \rst_n
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34"
+ wire width 11 \sram_addr
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39"
+ wire width 2 \sram_byte_n
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36"
+ wire \sram_ce_n
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35"
+ wire width 16 \sram_dq
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38"
+ wire \sram_oe_n
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61"
+ wire width 16 \sram_q
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
+ wire width 16 \sram_rdata
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+ wire width 16 \sram_wdata
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37"
+ wire \sram_we_n
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
+ wire \we_next
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48"
+ wire \write_dph
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+ process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
+ switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
+ case 1'1
+ case
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
+ switch \ahbls_hready
+ case 1'1
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
+ switch \ahbls_htrans [1]
+ case 1'1
+ case
+ end
+ case
+ attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+ switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
+ case 1'1
+ case
+ end
+ end
+ end
+ sync posedge \clk
+ sync negedge \rst_n
+ end
+ connect \ahbls_hresp 1'0
+ connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
+ connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
+ connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
+ connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
+ connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
+ connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
+ connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y }
+ connect \ahbls_hready_resp \hready_r
+end
+EOT
+
+synth_ice40 -abc2 -abc9
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 03:22:51 +0000