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-rw-r--r--tests/arch/ecp5/memories.ys2
-rw-r--r--tests/arch/ice40/memories.ys1
-rw-r--r--tests/opt/opt_expr_alu.ys74
-rw-r--r--tests/select/unset.ys10
-rw-r--r--tests/select/unset2.ys10
-rw-r--r--tests/various/abc9.ys19
-rw-r--r--tests/various/design.ys9
-rw-r--r--tests/various/design2.ys9
-rw-r--r--tests/various/global_scope.ys18
9 files changed, 141 insertions, 11 deletions
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index e1f748e26..f55bf01d2 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
-write_ilang
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:PDPW16KD # too inefficient
select -assert-min 18 t:LUT4
@@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
-write_ilang
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # too inefficient
select -assert-min 9 t:LUT4
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index 571edec1d..c32f12315 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-write_ilang
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # too inefficient
select -assert-min 1 t:SB_LUT4
diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys
index e288bcea6..9121c0096 100644
--- a/tests/opt/opt_expr_alu.ys
+++ b/tests/opt/opt_expr_alu.ys
@@ -8,7 +8,7 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
design -reset
@@ -20,7 +20,7 @@ EOT
alumacc
select -assert-count 1 t:$alu
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
design -reset
@@ -33,7 +33,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
design -reset
@@ -46,7 +46,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
design -reset
@@ -60,7 +60,8 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-count 1 t:$not
+select -assert-none t:$pos t:$not %% t:* %D
design -reset
@@ -76,7 +77,7 @@ design -load postopt
select -assert-count 1 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
select -assert-count 1 t:$not
-select -assert-count none t:$alu t:$not t:* %D %D
+select -assert-none t:$alu t:$not t:* %D %D
design -reset
@@ -93,7 +94,7 @@ dump
select -assert-count 2 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
design -reset
@@ -108,4 +109,61 @@ equiv_opt -assert opt -fine
design -load postopt
select -assert-count 2 t:$alu
select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+ .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+ .A_SIGNED(0), .B_SIGNED(0),
+) alu (
+ .A(a), .B(4'h0),
+ .BI(1'b0), .CI(1'b0),
+ .Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+ .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+ .A_SIGNED(0), .B_SIGNED(0),
+) alu (
+ .A(a), .B(4'h0),
+ .BI(1'b1), .CI(1'b1),
+ .Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+ .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+ .A_SIGNED(0), .B_SIGNED(0),
+) alu (
+ .A(4'h0), .B(a),
+ .BI(1'b0), .CI(1'b0),
+ .Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu
diff --git a/tests/select/unset.ys b/tests/select/unset.ys
new file mode 100644
index 000000000..4f60781c2
--- /dev/null
+++ b/tests/select/unset.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+select -set foo w:*
+select -assert-any @foo
+select -unset foo
+logger -expect error "Selection '\\foo' does not exist!" 1
+select -unset foo
diff --git a/tests/select/unset2.ys b/tests/select/unset2.ys
new file mode 100644
index 000000000..456b84c22
--- /dev/null
+++ b/tests/select/unset2.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+select -set foo w:*
+select -assert-any @foo
+select -unset foo
+logger -expect error "Selection @foo is not defined!" 1
+select -list @foo
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 0c7695089..6e2415ad7 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -53,3 +53,22 @@ assign q = w;
endmodule
EOT
abc9 -lut 4 -dff
+
+
+design -reset
+read_verilog -icells -specify <<EOT
+(* abc9_lut=1, blackbox *)
+module LUT2(input [1:0] i, output o);
+parameter [3:0] mask = 0;
+assign o = i[0] ? (i[1] ? mask[3] : mask[2])
+ : (i[1] ? mask[1] : mask[0]);
+specify
+ (i *> o) = 1;
+endspecify
+endmodule
+
+module top(input [1:0] i, output o);
+LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
+endmodule
+EOT
+abc9
diff --git a/tests/various/design.ys b/tests/various/design.ys
new file mode 100644
index 000000000..f13ad8171
--- /dev/null
+++ b/tests/various/design.ys
@@ -0,0 +1,9 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -delete foo
diff --git a/tests/various/design2.ys b/tests/various/design2.ys
new file mode 100644
index 000000000..399999020
--- /dev/null
+++ b/tests/various/design2.ys
@@ -0,0 +1,9 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -load foo
diff --git a/tests/various/global_scope.ys b/tests/various/global_scope.ys
new file mode 100644
index 000000000..8c8618e10
--- /dev/null
+++ b/tests/various/global_scope.ys
@@ -0,0 +1,18 @@
+read_verilog -sv <<EOT
+parameter A = 10;
+parameter B = A;
+
+typedef enum {
+ CONST_A = A,
+ CONST_B = A+1
+} enum_t;
+
+module top(output [3:0] q, output [3:0] r);
+assign q = 10;
+assign r = CONST_B;
+endmodule
+EOT
+
+hierarchy -top top
+sat -verify -prove q 10 top
+sat -verify -prove r 11 top
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-08 17:39:58 +0000