diff options
Diffstat (limited to 'tests')
69 files changed, 1158 insertions, 54 deletions
diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index 9a26bb8f4..b76bdb653 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1 +1,3 @@ /*_ref.v +/*.aag.log +/*.aig.log diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index 0bcc4e011..eb94177ad 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT2 -select -assert-count 5 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D +select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys index b419fb9bb..63df1ad5b 100644 --- a/tests/arch/ecp5/bug1630.ys +++ b/tests/arch/ecp5/bug1630.ys @@ -1,2 +1,2 @@ read_ilang bug1630.il.gz -abc9 -lut +/ecp5/abc9_5g.lut +abc9 -lut 4 diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index a2db2ad98..aef720d46 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 6 t:EFX_FF -select -assert-count 15 t:EFX_LUT4 +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys index fb9fccc3a..74319c480 100644 --- a/tests/arch/ice40/ice40_wrapcarry.ys +++ b/tests/arch/ice40/ice40_wrapcarry.ys @@ -50,5 +50,5 @@ select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i ice40_wrapcarry -unwrap -select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i -select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i +select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i +select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh index 5292d1615..170078a7f 100755 --- a/tests/arch/run-test.sh +++ b/tests/arch/run-test.sh @@ -2,12 +2,23 @@ set -e +declare -A defines=( ["ice40"]="ICE40_HX ICE40_LP ICE40_U" ) + echo "Running syntax check on arch sim models" for arch in ../../techlibs/*; do find $arch -name cells_sim.v | while read path; do - echo -n "Test $path ->" - iverilog -t null -I$arch $path - echo " ok" + arch_name=$(basename -- $arch) + if [ "${defines[$arch_name]}" ]; then + for def in ${defines[$arch_name]}; do + echo -n "Test $path -D$def ->" + iverilog -t null -I$arch -D$def $path + echo " ok" + done + else + echo -n "Test $path ->" + iverilog -t null -I$arch $path + echo " ok" + fi done done diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 70cfe81a3..6be9a73a3 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,11 +1,23 @@ read_verilog ../common/add_sub.v hierarchy -top top proc +design -save orig + equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 16 t:LUT2 +select -assert-count 8 t:LUT2 select -assert-count 2 t:CARRY4 select -assert-none t:LUT2 t:CARRY4 %% t:* %D +design -load orig + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +stat +select -assert-count 8 t:LUT2 +select -assert-count 6 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D diff --git a/tests/various/bug1480.ys b/tests/arch/xilinx/bug1480.ys index 84faea08a..84faea08a 100644 --- a/tests/various/bug1480.ys +++ b/tests/arch/xilinx/bug1480.ys diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index a464fcfdb..fec4c6082 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -3,6 +3,8 @@ hierarchy -top fsm proc flatten +design -save orig + equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter @@ -17,3 +19,20 @@ select -assert-count 1 t:LUT2 select -assert-count 3 t:LUT5 select -assert-count 1 t:LUT6 select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D + +design -load orig + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 1 t:LUT1 +select -assert-count 3 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 6 t:MUXF5 +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 3f127a77e..cc7354501 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -135,3 +135,23 @@ select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 2 t:RAM64M select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM16X1D +select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D diff --git a/tests/arch/xilinx/mux_lut4.ys b/tests/arch/xilinx/mux_lut4.ys new file mode 100644 index 000000000..3e3256993 --- /dev/null +++ b/tests/arch/xilinx/mux_lut4.ys @@ -0,0 +1,51 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 4 t:LUT1 +select -assert-count 2 t:MUXF5 +select -assert-count 1 t:MUXF6 + +select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D + + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 4 t:LUT1 +select -assert-count 3 t:LUT4 +select -assert-count 2 t:MUXF5 +select -assert-count 1 t:MUXF6 + +select -assert-none t:LUT1 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D + + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 32 t:LUT* +select -assert-max 8 t:MUXF6 +select -assert-max 4 t:MUXF7 + +select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh index 636aed12a..bd44395cb 100644 --- a/tests/arch/xilinx/tribuf.sh +++ b/tests/arch/xilinx/tribuf.sh @@ -1,5 +1,5 @@ -! ../../../yosys ../common/tribuf.v -qp "synth_xilinx" -../../../yosys ../common/tribuf.v -qp "synth_xilinx -iopad; \ +! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v +../../../yosys -qp "synth_xilinx -iopad; \ select -assert-count 2 t:IBUF; \ select -assert-count 1 t:INV; \ -select -assert-count 1 t:OBUFT" +select -assert-count 1 t:OBUFT" ../common/tribuf.v diff --git a/tests/memfile/.gitignore b/tests/memfile/.gitignore new file mode 100644 index 000000000..61b0d4264 --- /dev/null +++ b/tests/memfile/.gitignore @@ -0,0 +1 @@ +temp* diff --git a/tests/memfile/content1.dat b/tests/memfile/content1.dat new file mode 100644 index 000000000..4d1c67c26 --- /dev/null +++ b/tests/memfile/content1.dat @@ -0,0 +1,64 @@ +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 +00001111000000001111111100000000 diff --git a/tests/memfile/memory.v b/tests/memfile/memory.v new file mode 100644 index 000000000..57106eae8 --- /dev/null +++ b/tests/memfile/memory.v @@ -0,0 +1,23 @@ +// A memory initialized with an external file + +module memory ( + input clk_i, + input we_i, + input [5:0] addr_i, + input [31:0] data_i, + output reg [31:0] data_o +); + +parameter MEMFILE = ""; + +reg [31:0] mem [0:63]; + +initial $readmemb(MEMFILE,mem); + +always @(posedge clk_i) begin + if (we_i) + mem[addr_i] <= data_i; + data_o <= mem[addr_i]; +end + +endmodule diff --git a/tests/memfile/run-test.sh b/tests/memfile/run-test.sh new file mode 100755 index 000000000..e43ddd093 --- /dev/null +++ b/tests/memfile/run-test.sh @@ -0,0 +1,49 @@ +#!/bin/bash + +set -e + +mkdir -p temp +cp content1.dat temp/content2.dat + +cd .. + +echo "Running from the parent directory with content1.dat" +../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"content1.dat\" memory" +echo "Running from the parent directory with temp/content2.dat" +../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory" +echo "Running from the parent directory with memfile/temp/content2.dat" +../yosys -qp "read_verilog -defer memfile/memory.v; chparam -set MEMFILE \"memfile/temp/content2.dat\" memory" + +cd memfile + +echo "Running from the same directory with content1.dat" +../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"content1.dat\" memory" +echo "Running from the same directory with temp/content2.dat" +../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory" + +cd temp + +echo "Running from a child directory with content1.dat" +../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"content1.dat\" memory" +echo "Running from a child directory with temp/content2.dat" +../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory" +echo "Running from a child directory with content2.dat" +../../../yosys -qp "read_verilog -defer ../memory.v; chparam -set MEMFILE \"temp/content2.dat\" memory" + +cd .. + +echo "Checking a failure when zero length filename is provided" +if ../../yosys -qp "read_verilog memory.v"; then + echo "The execution should fail but it didn't happen, which is WRONG." + exit 1 +else + echo "Execution failed, which is OK." +fi + +echo "Checking a failure when not existing filename is provided" +if ../../yosys -qp "read_verilog -defer memory.v; chparam -set MEMFILE \"content3.dat\" memory"; then + echo "The execution should fail but it didn't happen, which is WRONG." + exit 1 +else + echo "Execution failed, which is OK." +fi diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys new file mode 100644 index 000000000..a3361ca43 --- /dev/null +++ b/tests/opt/opt_expr_alu.ys @@ -0,0 +1,63 @@ +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b0} + 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} + 1'b1; +endmodule +EOT + +alumacc +select -assert-count 1 t:$alu +select -assert-count none t:$alu t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys new file mode 100644 index 000000000..21439fd53 --- /dev/null +++ b/tests/opt/opt_expr_xor.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module top(input a, output [3:0] y); +assign y[0] = a^1'b0; +assign y[1] = 1'b1^a; +assign y[2] = a~^1'b0; +assign y[3] = 1'b1^~a; +endmodule +EOT +design -save read +select -assert-count 2 t:$xor +select -assert-count 2 t:$xnor + +equiv_opt opt_expr +design -load postopt +select -assert-none t:$xor +select -assert-none t:$xnor +select -assert-count 2 t:$not + + +design -load read +simplemap +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XOR_ +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 3 t:$_NOT_ + + +design -reset +read_verilog -icells <<EOT +module top(input a, output [1:0] y); +$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0])); +$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1])); +endmodule +EOT +select -assert-count 2 t:$_XNOR_ +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 1 t:$_NOT_ + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] w, x, y, z); +assign w = a^1'b0; +assign x = a^1'b1; +assign y = a~^1'b0; +assign z = a~^1'b1; +endmodule +EOT +equiv_opt opt_expr diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys index a29c29df6..0176f09c7 100644 --- a/tests/opt/opt_merge_init.ys +++ b/tests/opt/opt_merge_init.ys @@ -20,6 +20,7 @@ endmodule EOT opt_merge +select -assert-count 1 t:$dff select -assert-count 1 a:init=1'0 @@ -46,4 +47,31 @@ endmodule EOT opt_merge +select -assert-count 1 t:$dff select -assert-count 1 a:init=2'bx1 + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffo ( + .CLK(clk), + .D(i), + .Q(o) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffp ( + .CLK(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 2 t:$dff diff --git a/tests/opt/opt_merge_keep.ys b/tests/opt/opt_merge_keep.ys new file mode 100644 index 000000000..2a9202901 --- /dev/null +++ b/tests/opt/opt_merge_keep.ys @@ -0,0 +1,64 @@ +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + (* keep *) + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 a:keep + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + (* keep *) + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 a:keep + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + (* keep *) + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + (* keep *) + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 2 t:$_DFF_P_ +select -assert-count 2 a:keep diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py index eff41738a..8cbec5682 100644 --- a/tests/rpc/frontend.py +++ b/tests/rpc/frontend.py @@ -31,7 +31,7 @@ end import json import argparse -import sys, socket, os +import sys, socket, os, subprocess try: import msvcrt, win32pipe, win32file except ImportError: @@ -83,9 +83,11 @@ def main(): if args.mode == "unix-socket": sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM) + sock.settimeout(30) sock.bind(args.path) try: sock.listen(1) + ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)]) conn, addr = sock.accept() file = conn.makefile("rw") while True: @@ -93,7 +95,11 @@ def main(): if not input: break file.write(call(input) + "\n") file.flush() + ys_proc.wait(timeout=10) + if ys_proc.returncode: + raise subprocess.CalledProcessError(ys_proc.returncode, ys_proc.args) finally: + ys_proc.kill() sock.close() os.unlink(args.path) diff --git a/tests/rpc/run-test.sh b/tests/rpc/run-test.sh index 44ce7e674..eeb309347 100755 --- a/tests/rpc/run-test.sh +++ b/tests/rpc/run-test.sh @@ -4,3 +4,4 @@ for x in *.ys; do echo "Running $x.." ../../yosys -ql ${x%.ys}.log $x done +python3 frontend.py unix-socket frontend.sock diff --git a/tests/rpc/unix.ys b/tests/rpc/unix.ys deleted file mode 100644 index cc7ec14ab..000000000 --- a/tests/rpc/unix.ys +++ /dev/null @@ -1,6 +0,0 @@ -!python3 frontend.py unix-socket frontend.sock & sleep 0.1 -connect_rpc -path frontend.sock -read_verilog design.v -hierarchy -top top -flatten -select -assert-count 1 t:$neg diff --git a/tests/select/no_warn_assert.ys b/tests/select/no_warn_assert.ys new file mode 100644 index 000000000..889315826 --- /dev/null +++ b/tests/select/no_warn_assert.ys @@ -0,0 +1,2 @@ +logger -expect-no-warnings +select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i diff --git a/tests/select/no_warn_prefixed_arg_memb.ys b/tests/select/no_warn_prefixed_arg_memb.ys new file mode 100644 index 000000000..596a6ed70 --- /dev/null +++ b/tests/select/no_warn_prefixed_arg_memb.ys @@ -0,0 +1,5 @@ +logger -expect-no-warnings +read_verilog ../../examples/igloo2/example.v +hierarchy +proc +select example/t:$add diff --git a/tests/select/no_warn_prefixed_empty_select_arg.ys b/tests/select/no_warn_prefixed_empty_select_arg.ys new file mode 100644 index 000000000..617e0d63e --- /dev/null +++ b/tests/select/no_warn_prefixed_empty_select_arg.ys @@ -0,0 +1,3 @@ +logger -expect-no-warnings +select n:foo/bar* +select t:$assert diff --git a/tests/select/run-test.sh b/tests/select/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/select/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done diff --git a/tests/select/warn_empty_select_arg.ys b/tests/select/warn_empty_select_arg.ys new file mode 100644 index 000000000..55aca8eb6 --- /dev/null +++ b/tests/select/warn_empty_select_arg.ys @@ -0,0 +1,3 @@ +logger -expect warning "did not match any module." 1 +logger -expect warning "did not match any object." 1 +select foo/bar diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v new file mode 100644 index 000000000..7236ac3a5 --- /dev/null +++ b/tests/simple/dynslice.v @@ -0,0 +1,12 @@ +module dynslice ( + input clk , + input [9:0] ctrl , + input [15:0] din , + input [3:0] sel , + output reg [127:0] dout +); +always @(posedge clk) +begin + dout[ctrl*sel+:16] <= din ; +end +endmodule diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 7461358ad..83493fcb0 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -60,3 +60,7 @@ always @(posedge clk) begin end endmodule + +module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout); +assign dout = din[a*b +: 2]; +endmodule diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box deleted file mode 100644 index a8801d807..000000000 --- a/tests/simple_abc9/abc.box +++ /dev/null @@ -1,2 +0,0 @@ -MUXF8 1 0 3 1 -1 1 1 diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index e5837d480..688b47586 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1, whitebox *) +(* abc9_box, blackbox *) module MUXF8(input I0, I1, S, output O); +specify + (I0 => O) = 0; + (I1 => O) = 0; + (S => O) = 0; +endspecify endmodule // Citation: https://github.com/alexforencich/verilog-ethernet diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 32d7a80ca..424d8f417 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,8 +25,8 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4 -box ../abc.box; \ + abc9 -lut 4; \ clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ - setattr -mod -unset whitebox'" + setattr -mod -unset blackbox'" diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv new file mode 100644 index 000000000..4e4d5871c --- /dev/null +++ b/tests/svtypes/enum_simple.sv @@ -0,0 +1,48 @@ + +module enum_simple(input clk, input rst); + + enum {s0, s1, s2, s3} test_enum; + typedef enum logic [1:0] { + ts0, ts1, ts2, ts3 + } states_t; + states_t state; + (states_t) state1; + states_t enum_const = ts1; + + always @(posedge clk) begin + if (rst) begin + test_enum <= s3; + state <= ts0; + end else begin + //test_enum + if (test_enum == s0) + test_enum <= s1; + else if (test_enum == s1) + test_enum <= s2; + else if (test_enum == s2) + test_enum <= s3; + else if (test_enum == s3) + test_enum <= s0; + else + assert(1'b0); //should be unreachable + + //state + if (state == ts0) + state <= ts1; + else if (state == ts1) + state <= ts2; + else if (state == ts2) + state <= ts0; + else + assert(1'b0); //should be unreachable + end + end + + always @(*) begin + assert(state != 2'h3); + assert(s0 == '0); + assert(ts0 == '0); + assert(enum_const == ts1); + end + +endmodule diff --git a/tests/svtypes/enum_simple.ys b/tests/svtypes/enum_simple.ys new file mode 100644 index 000000000..79981657b --- /dev/null +++ b/tests/svtypes/enum_simple.ys @@ -0,0 +1,5 @@ + +read_verilog -sv enum_simple.sv +hierarchy; proc; opt +sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all + diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index 577e484ad..37e63c1d0 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] ram16x4_t[0:15]; - (ram16x4_t) mem; + ram16x4_t mem; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index f3089bf55..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] nibble; - (nibble) mem[0:15]; + nibble mem[0:15]; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index a1e16d4b1..57a78c53a 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -1,11 +1,14 @@ package pkg; typedef logic [7:0] uint8_t; + typedef enum logic [7:0] {bb=8'hBB} enum8_t; endpackage module top; - (* keep *) (pkg::uint8_t) a = 8'hAA; + (* keep *) pkg::uint8_t a = 8'hAA; + (* keep *) pkg::enum8_t b_enum = pkg::bb; always @* assert(a == 8'hAA); + always @* assert(b_enum == 8'hBB); endmodule diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index ddbd471e0..d838dd828 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -6,12 +6,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef (int8_t) char_t; + typedef int8_t char_t; - parameter (uint2_t) int2 = 2'b10; - localparam (int4_t) int4 = -1; - localparam (int8_t) int8 = int4; - localparam (char_t) ch = int8; + parameter uint2_t int2 = 2'b10; + localparam int4_t int4 = -1; + localparam int8_t int8 = int4; + localparam char_t ch = int8; `STATIC_ASSERT(int2 == 2'b10); diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index faa385bd6..5507d84f2 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -1,23 +1,42 @@ typedef logic [3:0] outer_uint4_t; +typedef enum logic {s0, s1} outer_enum_t; module top; - (outer_uint4_t) u4_i = 8'hA5; + outer_uint4_t u4_i = 8'hA5; + outer_enum_t enum4_i = s0; always @(*) assert(u4_i == 4'h5); + always @(*) assert(enum4_i == 1'b0); typedef logic [3:0] inner_type; - (inner_type) inner_i1 = 8'h5A; + typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t; + inner_type inner_i1 = 8'h5A; + inner_enum_t inner_enum1 = s3; always @(*) assert(inner_i1 == 4'hA); + always @(*) assert(inner_enum1 == 3'h3); if (1) begin: genblock typedef logic [7:0] inner_type; - (inner_type) inner_gb_i = 8'hA5; + parameter inner_type inner_const = 8'hA5; + typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t; + inner_type inner_gb_i = inner_const; //8'hA5; + inner_enum_t inner_gb_enum1 = s7; always @(*) assert(inner_gb_i == 8'hA5); + always @(*) assert(inner_gb_enum1 == 3'h7); end - (inner_type) inner_i2 = 8'h42; + inner_type inner_i2 = 8'h42; + inner_enum_t inner_enum2 = s4; always @(*) assert(inner_i2 == 4'h2); + always @(*) assert(inner_enum2 == 3'h4); +endmodule + +typedef logic[7:0] between_t; +module other; + between_t a = 8'h42; + always @(*) assert(a == 8'h42); endmodule + diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 7e760dee4..8f89910e5 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -3,12 +3,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef (int8_t) char_t; + typedef int8_t char_t; - (* keep *) (uint2_t) int2 = 2'b10; - (* keep *) (int4_t) int4 = -1; - (* keep *) (int8_t) int8 = int4; - (* keep *) (char_t) ch = int8; + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; always @* assert(int2 == 2'b10); diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys new file mode 100644 index 000000000..7c8a63692 --- /dev/null +++ b/tests/techmap/cmp2lcu.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +assign gtu = a > b; +assign gts = $signed(a) > $signed(b); +assign ltu = a < b; +assign lts = $signed(a) < $signed(b); +assign geu = a >= b; +assign ges = $signed(a) >= $signed(b); +assign leu = a <= b; +assign les = $signed(a) <= $signed(b); +endmodule +EOT + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=5 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=7 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + + +design -reset +read_verilog <<EOT +module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]}; +wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]}; +assign gtu = c > d; +assign gts = $signed(c) > $signed(d); +assign ltu = c < d; +assign lts = $signed(c) < $signed(d); +assign geu = c >= d; +assign ges = $signed(c) >= $signed(d); +assign leu = c <= d; +assign les = $signed(c) <= $signed(d); +endmodule +EOT +design -save gold + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=2 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=4 %i +select -assert-none t:$gt t:$ge t:$lt t:$le diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index c058d1607..df029b3a0 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -4,12 +4,15 @@ module obuf (input i, (* iopad_external_pin *) output o); endmodule module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule +module buf_inside (input i, output o); +obuf b (.i(i), .o(o)); +endmodule + module a(input i, output o); assign o = i; endmodule module b(input i, output o); -assign o = i; ibuf b (.i(i), .o(o)); endmodule @@ -42,13 +45,29 @@ assign io = i; assign o = io; endmodule +module i(input i, output o); +buf_inside b (.i(i), .o(o)); +endmodule + +module j(input i, output o); +wire tmp; +obuf b (.i(i), .o(tmp)); +assign o = tmp; +endmodule + +module k(inout o, o2); +assign o = 1'bz; +endmodule + EOT opt_clean tribuf simplemap -iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io +iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j k opt_clean +hierarchy -check +check select -assert-count 1 a/t:ibuf select -assert-count 1 a/t:obuf @@ -120,3 +139,48 @@ select -assert-count 1 g/t:iobuf select -assert-count 1 h/t:ibuf select -assert-count 1 h/t:iobuf select -assert-count 1 h/t:obuf + +select -assert-count 1 i/t:ibuf +select -assert-count 0 i/t:obuf + +select -assert-count 1 j/t:ibuf +select -assert-count 1 j/t:obuf + +select -assert-count 2 k/t:iobuf + + +# Check that \init attributes get moved from output buffer +# to buffer input +design -reset +read_verilog << EOT +module obuf (input i, (* iopad_external_pin *) output o); endmodule +module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule +module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule +module sub(input i, output o); endmodule + +module a(input i, (* init=1'b1 *) output o); +sub s(.i(i), .o(o)); +endmodule + +module b(input [1:0] i, oe, (* init=2'b1x *) output [1:0] o); +wire [1:0] w; +sub s1(.i(i[0]), .o(w[0])); +sub s2(.i(i[1]), .o(w[1])); +assign o = oe ? w : 2'bz; +endmodule + +module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2); +assign io = oe ? i : 1'bz; +assign {o1,o2} = {io,io}; +endmodule +EOT +opt_clean +tribuf +simplemap +iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io +select -assert-count 1 a/c:s %co a/a:init=1'b1 %i +select -assert-count 1 a/a:init +select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i +select -assert-count 1 b/a:init +select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i +select -assert-count 1 c/a:init diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index c2f42d50b..8403586bd 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -16,3 +16,21 @@ EOT techmap -map %techmap select -assert-any w:s0.asdf select -assert-any c:s0.blah + +read_verilog <<EOT +module sub(input i, output o, input j); +wire _TECHMAP_REPLACE_.asdf = i ; +barfoo _TECHMAP_REPLACE_.blah (i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +select -assert-any w:s0.asdf +select -assert-any c:s0.blah diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 4b286fd61..12d4e5048 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -3,3 +3,4 @@ /write_gzip.v /write_gzip.v.gz /run-test.mk +/plugin.so diff --git a/tests/various/bug1614.ys b/tests/various/bug1614.ys new file mode 100644 index 000000000..6fbe84a4c --- /dev/null +++ b/tests/various/bug1614.ys @@ -0,0 +1,5 @@ +read_verilog <<EOT +module testcase; + wire [3:0] #1 a = 4'b0000; +endmodule +EOT diff --git a/tests/various/bug1710.ys b/tests/various/bug1710.ys new file mode 100644 index 000000000..c2ecf3c90 --- /dev/null +++ b/tests/various/bug1710.ys @@ -0,0 +1,30 @@ +logger -werror "out of bounds" +read_verilog <<EOT +module Example; + + parameter FLAG = 1; + wire [3:0] inp; + + reg out1; + initial out1 = FLAG ? &inp[2:0] : &inp[4:0]; + + reg out2; + initial + if (FLAG) + out2 = &inp[2:0]; + else + out2 = &inp[4:0]; + + wire out3; + assign out3 = FLAG ? &inp[2:0] : &inp[4:0]; + + wire out4; + generate + if (FLAG) + assign out4 = &inp[2:0]; + else + assign out4 = &inp[4:0]; + endgenerate + +endmodule +EOT diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys new file mode 100644 index 000000000..2e5b8c2d4 --- /dev/null +++ b/tests/various/bug1745.ys @@ -0,0 +1,8 @@ +logger -expect error "syntax error, unexpected TOK_CONSTVAL" 1 +read_verilog <<EOT +module inverter(input a, output y); + + assign y = (a == 1'b0? 1'b1 : 1'b0); + +endmodule // inverter +EOT diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys new file mode 100644 index 000000000..60dcc0830 --- /dev/null +++ b/tests/various/bug1781.ys @@ -0,0 +1,33 @@ +read_verilog <<EOT + +module top(input clk, input rst); + +reg [1:0] state; + +always @(posedge clk, posedge rst) begin + if (rst) + state <= 0; + else + case (state) + 2'b00: state <= 2'b01; + 2'b01: state <= 2'b10; + 2'b10: state <= 2'b00; + endcase +end + +sub sub_i(.i(state == 0)); + +endmodule + + +(* blackbox, keep *) +module sub(input i); +endmodule + +EOT + +proc +fsm + +# Make sure there is a driver +select -assert-any t:sub %ci %a w:* %i %ci c:* %i diff --git a/tests/various/constcomment.ys b/tests/various/constcomment.ys new file mode 100644 index 000000000..f4f2e75d8 --- /dev/null +++ b/tests/various/constcomment.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top1; + localparam a = 8 /*foo*/ 'h ab; + localparam b = 8 'h /*foo*/ cd; + generate + if (a != 8'b10101011) $error("a incorrect!"); + if (b != 8'b11001101) $error("b incorrect!"); + endgenerate +endmodule +EOT +logger -expect error "syntax error, unexpected TOK_BASE" 1 +read_verilog <<EOT +module top2; + localparam a = 12'h4 /*foo*/'b0; +endmodule +EOT diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys new file mode 100644 index 000000000..5ed00509d --- /dev/null +++ b/tests/various/deminout_unused.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT +module top(input clk, inout [7:0] x); + +reg [3:0] ctr; +always @(posedge clk) ctr <= ctr + 1'b1; + +assign x[7:4] = ctr; +endmodule +EOT +proc +tribuf +deminout +select -assert-count 1 i:x o:x %i + diff --git a/tests/various/exec.ys b/tests/various/exec.ys new file mode 100644 index 000000000..0eec00719 --- /dev/null +++ b/tests/various/exec.ys @@ -0,0 +1,6 @@ +exec -expect-return 0 -- exit 0 +exec -expect-return 27 -- exit 27 +exec -expect-stdout nana -expect-stdout api -not-expect-stdout giraffe -- echo "bananapie" + +logger -expect error "stdout did have a line" 1 +exec -not-expect-stdout giraffe -- echo "giraffe" diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys index 85d6267c5..ba94787bc 100644 --- a/tests/various/mem2reg.ys +++ b/tests/various/mem2reg.ys @@ -9,6 +9,6 @@ EOT proc cd top -select -assert-count 1 m:data1 a:src=<<EOT:4 %i -select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i +select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i +select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i select -assert-none a:mem2reg diff --git a/tests/various/plugin.cc b/tests/various/plugin.cc new file mode 100644 index 000000000..be305fbda --- /dev/null +++ b/tests/various/plugin.cc @@ -0,0 +1,15 @@ +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +struct TestPass : public Pass { + TestPass() : Pass("test", "test") { } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx = 1; + extra_args(args, argidx, design); + log("Plugin test passed!\n"); + } +} TestPass; + +YOSYS_NAMESPACE_END diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh new file mode 100644 index 000000000..d6d4aee59 --- /dev/null +++ b/tests/various/plugin.sh @@ -0,0 +1,6 @@ +set -e +rm -f plugin.so +CXXFLAGS=$(../../yosys-config --cxxflags) +CXXFLAGS=${CXXFLAGS// -I\/usr\/local\/share\/yosys\/include/ -I..\/..\/share\/include} +../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc +../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!" diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v index 563394080..c1994e92c 100644 --- a/tests/various/pmux2shiftx.v +++ b/tests/various/pmux2shiftx.v @@ -33,7 +33,7 @@ module pmux2shiftx_test ( end endmodule -module issue01135(input [7:0] i, output o); +module issue01135(input [7:0] i, output reg o); always @* case (i[6:3]) 4: o <= i[0]; diff --git a/tests/various/specify.v b/tests/various/specify.v index 5d44d78f7..c160d2ec4 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,11 +7,9 @@ module test ( if (EN) Q <= D; specify -`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); -`endif endspecify endmodule @@ -37,3 +35,30 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test3(input clk, input [1:0] d, output [1:0] q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule + +module test4(input clk, d, output q); +specify + $setup(d, posedge clk, 1:2:3); + $setuphold(d, posedge clk, 1:2:3, 4:5:6); +endspecify +endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule + +module test6(input clk, d, e, output q); +specify + (d[0] *> q[0]) = (3,1); + (posedge clk[0] => (q[0] +: d[0])) = (3,1); +endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 00597e1e2..9d55b8eb5 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,23 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v +read_verilog -specify <<EOT +(* blackbox *) +module test7_sub(input i, output o); +specify + (i => o) = 1; +endspecify +assign o = ~i; +endmodule + +module test7(input i, output o); + wire w; + test7_sub unused(i, w); + test7_sub used(i, o); +endmodule +EOT +hierarchy +cd test7 +clean +select -assert-count 1 c:used +select -assert-none c:* c:used %d diff --git a/tests/various/src.ys b/tests/various/src.ys new file mode 100644 index 000000000..89d6700ca --- /dev/null +++ b/tests/various/src.ys @@ -0,0 +1,8 @@ +logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1 +logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1 +read_verilog <<EOT +module top(input i, output o, p); +always @* o <= i; +always @* p = i; +endmodule +EOT diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..4fb45043b --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,124 @@ +read_verilog <<EOT +module top(input a, output b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b); +(* submod="bar" *) sub s1(a, b[1]); +assign b[0] = 1'b0; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b, c); +(* submod="bar" *) sub s1(a, b[0]); +(* submod="bar" *) sub s2(a, c[1]); +assign c = b; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule + +module DFF(input D, C, output Q); +parameter INIT = 1'b0; +endmodule +EOT + +hierarchy -top top +proc + +submod +dffinit -ff DFF Q INIT +check -noinit -assert + + +design -reset +read_verilog <<EOT +module top(input d, c, output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule +EOT + +hierarchy -top top +proc + +submod +flatten + +read_verilog <<EOT +module DFF(input D, C, output Q); +endmodule +EOT + +check -assert diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys new file mode 100644 index 000000000..8e70ee0ee --- /dev/null +++ b/tests/various/sv_defines.ys @@ -0,0 +1,33 @@ +# Check that basic macro expansions do what you'd expect + +read_verilog <<EOT +`define empty_arglist() 123 +`define one_arg(x) 123+x +`define opt_arg(x = 1) 123+x +`define two_args(x, y = (1+23)) x+y +`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y + +module top; + localparam a = `empty_arglist(); + localparam b = `one_arg(10); + localparam c = `opt_arg(10); + localparam d = `opt_arg(); + localparam e = `two_args(1,2); + localparam f = `two_args(1); + localparam g = `nested_comma(1, 2); + localparam h = `nested_comma({31'b0, (1'b0)}); + localparam i = `nested_comma(, 1); + + generate + if (a != 123) $error("a bad"); + if (b != 133) $error("b bad"); + if (c != 133) $error("c bad"); + if (d != 124) $error("d bad"); + if (e != 3) $error("e bad"); + if (f != 25) $error("f bad"); + if (g != 3) $error("g bad"); + if (h != 3) $error("h bad"); + if (i != 2) $error("i bad"); + endgenerate +endmodule +EOT diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys new file mode 100644 index 000000000..38418ba8f --- /dev/null +++ b/tests/various/sv_defines_dup.ys @@ -0,0 +1,5 @@ +# Check for duplicate arguments +logger -expect error "Duplicate macro arguments with name `x'" 1 +read_verilog <<EOT +`define duplicate_arg(x, x) +EOT diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys new file mode 100644 index 000000000..ab6e899de --- /dev/null +++ b/tests/various/sv_defines_mismatch.ys @@ -0,0 +1,5 @@ +# Check that we spot mismatched brackets +logger -expect error "Mismatched brackets in macro argument: \[ and }." 1 +read_verilog <<EOT +`define foo(x=[1,2}) +EOT diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys new file mode 100644 index 000000000..295884809 --- /dev/null +++ b/tests/various/sv_defines_too_few.ys @@ -0,0 +1,7 @@ +# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no" +# arguments actually passes 1 empty argument). +logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1 +read_verilog <<EOT +`define foo(x=1, y) +`foo() +EOT |