diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/adffs.v | 20 | ||||
| -rw-r--r-- | tests/ice40/adffs.ys | 13 | ||||
| -rwxr-xr-x | tests/ice40/run-test.sh | 2 | ||||
| -rw-r--r-- | tests/techmap/wireinit.ys | 14 |
4 files changed, 27 insertions, 22 deletions
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 93c8bf52c..09dc36001 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,29 +22,25 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk, posedge pre ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) + always @( negedge clk, negedge pre ) + if ( !pre ) q <= 1'b1; else q <= d; @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 14b251c5c..548060b66 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,11 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFN -select -assert-count 2 t:SB_DFFSR -select -assert-count 7 t:SB_LUT4 -select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys index 1396839fe..89afaafb5 100644 --- a/tests/techmap/wireinit.ys +++ b/tests/techmap/wireinit.ys @@ -46,11 +46,13 @@ input clk; input d; output reg q0 = 0; output reg q1 = 1; +output reg qq0 = 0; output reg qx; always @(posedge clk) begin q0 <= d; q1 <= d; + qq0 <= q0; qx <= d; end endmodule @@ -64,16 +66,20 @@ simplemap techmap -map %map clean # Make sure the parameter was used properly. -select -assert-count 2 top/t:ffbb +select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i +select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 +select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i +select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are dropped from the wires iff mapping was performed. select -assert-count 0 top/w:q0 a:init %i +select -assert-count 0 top/w:qq0 a:init %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i @@ -84,15 +90,19 @@ simplemap techmap -map %map_noremove clean # Make sure the parameter was used properly. -select -assert-count 2 top/t:ffbb +select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i +select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 +select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i +select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are not dropped from the wires. select -assert-count 1 top/w:q0 a:init=1'b0 %i +select -assert-count 1 top/w:qq0 a:init=1'b0 %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i |