diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/intel_alm/blockram.ys | 3 | ||||
| -rw-r--r-- | tests/sat/grom_cpu.v | 2 | ||||
| -rw-r--r-- | tests/sat/ram_memory.v | 2 | ||||
| -rw-r--r-- | tests/various/.gitignore | 1 | ||||
| -rw-r--r-- | tests/various/json_escape_chars.ys | 14 |
5 files changed, 20 insertions, 2 deletions
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys index c157c3165..3b61b9339 100644 --- a/tests/arch/intel_alm/blockram.ys +++ b/tests/arch/intel_alm/blockram.ys @@ -2,5 +2,6 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp synth_intel_alm -family cyclonev -noiopad -noclkbuf cd sync_ram_sdp +select -assert-count 1 t:MISTRAL_NOT select -assert-count 1 t:MISTRAL_M10K -select -assert-none t:MISTRAL_M10K %% t:* %D +select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v index f9fef043b..914c0f56c 100644 --- a/tests/sat/grom_cpu.v +++ b/tests/sat/grom_cpu.v @@ -185,7 +185,7 @@ module grom_cpu( `ifdef DISASSEMBLY $display("INC R%d",IR[1:0]); `endif - alu_op <= 4'b0001; // ALU_OP_ADD + alu_op <= 4'b0000; // ALU_OP_ADD end 2'b01 : begin `ifdef DISASSEMBLY diff --git a/tests/sat/ram_memory.v b/tests/sat/ram_memory.v index 053ef206c..0d91514b2 100644 --- a/tests/sat/ram_memory.v +++ b/tests/sat/ram_memory.v @@ -27,6 +27,8 @@ module ram_memory( store[256] <= 8'b11010001; // OUT [0],R1 store[257] <= 8'b00000000; // store[258] <= 8'b01111110; // RET + + store[512] <= 8'b00000000; end always @(posedge clk) diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 2bb6c7179..c6373468a 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -5,3 +5,4 @@ /run-test.mk /plugin.so /plugin.so.dSYM +/temp diff --git a/tests/various/json_escape_chars.ys b/tests/various/json_escape_chars.ys new file mode 100644 index 000000000..f118357c0 --- /dev/null +++ b/tests/various/json_escape_chars.ys @@ -0,0 +1,14 @@ +! mkdir -p temp +read_verilog <<EOT +(* src = "\042 \057 \134 \010 \014 \012 \015 \011 \025 \033" *) +module foo; +endmodule +EOT +write_json temp/test_escapes.json +design -reset +read_json temp/test_escapes.json +write_json temp/test_escapes.json +design -reset +read_json temp/test_escapes.json +write_rtlil temp/test_escapes.json.il +! grep -F 'attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"' temp/test_escapes.json.il |