18 files changed, 142 insertions, 38 deletions

diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh
index cf506470d..fbdcbf048 100755
--- a/tests/fsm/run-test.sh
+++ b/tests/fsm/run-test.sh
@@ -6,7 +6,7 @@
 set -e
 
 OPTIND=1
-count=100
+count=50
 seed=""    # default to no seed specified
 while getopts "c:S:" opt
 do
diff --git a/tests/opt/opt_rmdff.ys b/tests/opt/opt_rmdff.ys
index 081f81782..83a162f44 100644
--- a/tests/opt/opt_rmdff.ys
+++ b/tests/opt/opt_rmdff.ys
@@ -19,8 +19,8 @@ hierarchy -top equiv
 equiv_simple -undef
 equiv_status -assert
 
-design -load gold
-stat
-
-design -load gate
-stat
+#design -load gold
+#stat
+#
+#design -load gate
+#stat
diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/proc/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v
new file mode 100644
index 000000000..698ac937a
--- /dev/null
+++ b/tests/proc/bug_1268.v
@@ -0,0 +1,23 @@
+module gold (input clock, ctrl, din, output reg dout);
+	always @(posedge clock) begin
+		if (1'b1) begin
+			if (1'b0) begin end else begin
+				dout <= 0;
+			end
+			if (ctrl)
+				dout <= din;
+		end
+	end
+endmodule
+
+module gate (input clock, ctrl, din, output reg dout);
+	always @(posedge clock) begin
+		if (1'b1) begin
+			if (1'b0) begin end else begin
+				dout <= 0;
+			end
+		end
+		if (ctrl)
+			dout <= din;
+	end
+endmodule
diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys
new file mode 100644
index 000000000..b73e94449
--- /dev/null
+++ b/tests/proc/bug_1268.ys
@@ -0,0 +1,5 @@
+read_verilog bug_1268.v
+proc
+equiv_make gold gate equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/proc/run-test.sh b/tests/proc/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/proc/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v
index 5b756e6be..74ed8faa5 100644
--- a/tests/simple/realexpr.v
+++ b/tests/simple/realexpr.v
@@ -1,4 +1,3 @@
-
 module demo_001(y1, y2, y3, y4);
 	output [7:0] y1, y2, y3, y4;
 
@@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3);
 	assign y3 = 1 ? -1 : 'd0;
 endmodule
 
+module demo_003(output A, B);
+	parameter real p = 0;
+	assign A = (p==1.0);
+	assign B = (p!="1.000000");
+endmodule
+
+module demo_004(output A, B, C, D);
+	demo_003 #(1.0) demo_real (A, B);
+	demo_003 #(1) demo_int (C, D);
+endmodule
diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore
index 598951333..2355aea29 100644
--- a/tests/simple_abc9/.gitignore
+++ b/tests/simple_abc9/.gitignore
@@ -1,3 +1,4 @@
 *.v
+*.sv
 *.log
 *.out
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 4935d41ad..49ae23338 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,5 +18,6 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
+cp ../simple/*.sv .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v
new file mode 100644
index 000000000..d281b21d8
--- /dev/null
+++ b/tests/techmap/recursive.v
@@ -0,0 +1,8 @@
+module top;
+sub s0();
+foo f0();
+endmodule
+
+module foo;
+sub s0();
+endmodule
diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v
new file mode 100644
index 000000000..934256552
--- /dev/null
+++ b/tests/techmap/recursive_map.v
@@ -0,0 +1,4 @@
+module sub;
+    sub _TECHMAP_REPLACE_ ();
+    bar f0();
+endmodule
diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh
new file mode 100644
index 000000000..30c79bf03
--- /dev/null
+++ b/tests/techmap/recursive_runtest.sh
@@ -0,0 +1,3 @@
+set -ev
+
+../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
index 31078b298..4b286fd61 100644
--- a/tests/various/.gitignore
+++ b/tests/various/.gitignore
@@ -2,3 +2,4 @@
 /*.out
 /write_gzip.v
 /write_gzip.v.gz
+/run-test.mk
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys
new file mode 100644
index 000000000..00389c700
--- /dev/null
+++ b/tests/various/mem2reg.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top;
+parameter DATADEPTH=2;
+parameter DATAWIDTH=1;
+(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
+(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
+endmodule
+EOT
+
+proc
+cd top
+select -assert-count 1 m:data1 a:src=<<EOT:4 %i
+select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index af23fcec8..3e90419af 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,7 +6,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -21,7 +21,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -52,7 +52,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -67,7 +67,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -82,7 +82,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -97,7 +97,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -112,7 +112,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -127,7 +127,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -142,7 +142,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 7 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -157,7 +157,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 4 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -172,7 +172,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 3 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -204,7 +204,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -222,7 +222,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -240,7 +240,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -258,7 +258,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
diff --git a/tests/various/pmgen_reduce.ys b/tests/various/pmgen_reduce.ys
new file mode 100644
index 000000000..c214d3f25
--- /dev/null
+++ b/tests/various/pmgen_reduce.ys
@@ -0,0 +1,21 @@
+test_pmgen -generate reduce
+hierarchy -top pmtest_test_pmgen_pm_reduce
+flatten; opt_clean
+
+design -save gold
+test_pmgen -reduce_chain
+design -stash gate
+
+design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
+design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts miter
+
+design -load gold
+test_pmgen -reduce_tree
+design -stash gate
+
+design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
+design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts miter
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 92b905765..ea56b70f0 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,12 +1,20 @@
 #!/usr/bin/env bash
 set -e
+{
+echo "all::"
 for x in *.ys; do
-	echo "Running $x.."
-	../../yosys -ql ${x%.ys}.log $x
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-		echo "Running $s.."
-		bash $s
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
 	fi
 done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index d644a88aa..0e5fe882b 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -11,7 +11,7 @@ shregmap -init
 
 opt
 
-stat
+# stat
 # show -width
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__SHREG_DFF_P_
@@ -26,11 +26,11 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+#design -load gold
+#stat
 
-design -load gate
-stat
+#design -load gate
+#stat
 
 ##########
 
@@ -43,9 +43,9 @@ design -save gold
 simplemap t:$dff t:$dffe
 shregmap -tech xilinx
 
-stat
+#stat
 # show -width
-write_verilog -noexpr -norename
+# write_verilog -noexpr -norename
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__XILINX_SHREG_
 
@@ -59,8 +59,8 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+# design -load gold
+# stat
 
-design -load gate
-stat
+# design -load gate
+# stat