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-rw-r--r--tests/opt/opt_ff_sat.v12
-rw-r--r--tests/opt/opt_ff_sat.ys5
2 files changed, 17 insertions, 0 deletions
diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v
new file mode 100644
index 000000000..5a0a6fe37
--- /dev/null
+++ b/tests/opt/opt_ff_sat.v
@@ -0,0 +1,12 @@
+module top (
+ input clk,
+ output reg [7:0] cnt
+);
+ initial cnt = 0;
+ always @(posedge clk) begin
+ if (cnt < 20)
+ cnt <= cnt + 1;
+ else
+ cnt <= 0;
+ end
+endmodule
diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys
new file mode 100644
index 000000000..4e7cc6ca4
--- /dev/null
+++ b/tests/opt/opt_ff_sat.ys
@@ -0,0 +1,5 @@
+read_verilog opt_ff_sat.v
+prep -flatten
+opt_rmdff -sat
+synth
+select -assert-count 5 t:$_DFF_P_