diff options
Diffstat (limited to 'tests')
71 files changed, 1652 insertions, 149 deletions
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index deaf48a3d..8e932b091 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -33,7 +33,7 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 16 miter -" +" -l ${aag}.log done for aig in *.aig; do @@ -50,5 +50,5 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 16 miter -" +" -l ${aig}.log done diff --git a/tests/aiger/symbols.aag b/tests/aiger/symbols.aag new file mode 100644 index 000000000..93f8989f2 --- /dev/null +++ b/tests/aiger/symbols.aag @@ -0,0 +1,9 @@ +aag 2 1 1 1 0 +2 +4 2 1 +4 +i0 d +l0 q +o0 q +c +Generated by Yosys 0.9+932 (git sha1 baba33fb, clang 9.0.0-2 -fPIC -Os) diff --git a/tests/aiger/symbols.aig b/tests/aiger/symbols.aig new file mode 100644 index 000000000..a7922ab46 --- /dev/null +++ b/tests/aiger/symbols.aig @@ -0,0 +1,8 @@ +aig 2 1 1 1 0 +2 1 +4 +i0 d +l0 q +o0 q +c +Generated by Yosys 0.9+932 (git sha1 baba33fb, clang 9.0.0-2 -fPIC -Os) diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index d363ec24e..a6eab248c 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/lutram.ys index 87b93c2fe..9ebb75443 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic @@ -11,7 +11,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:AL_MAP_LUT2 select -assert-count 8 t:AL_MAP_LUT4 diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/blockram.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/common/lutram.v b/tests/arch/common/lutram.v new file mode 100644 index 000000000..9534b7619 --- /dev/null +++ b/tests/arch/common/lutram.v @@ -0,0 +1,42 @@ +module lutram_1w1r +#(parameter D_WIDTH=8, A_WIDTH=6) +( + input [D_WIDTH-1:0] data_a, + input [A_WIDTH:1] addr_a, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + end +endmodule + + +module lutram_1w3r +#(parameter D_WIDTH=8, A_WIDTH=5) +( + input [D_WIDTH-1:0] data_a, data_b, data_c, + input [A_WIDTH:1] addr_a, addr_b, addr_c, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a, q_b, q_c +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + q_b <= ram[addr_b]; + q_c <= ram[addr_c]; + end +endmodule diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/common/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/common/memory_attributes/attributes_test.v b/tests/arch/common/memory_attributes/attributes_test.v new file mode 100644 index 000000000..275800dd0 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.v @@ -0,0 +1,88 @@ +`default_nettype none +module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // block_ram + +`default_nettype none +module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys new file mode 100644 index 000000000..1142ae0b5 --- /dev/null +++ b/tests/arch/ecp5/bug1459.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module register_file( + input wire clk, + input wire write_enable, + input wire [63:0] write_data, + input wire [4:0] write_reg, + input wire [4:0] read1_reg, + output reg [63:0] read1_data, + ); + + reg [63:0] registers[0:31]; + + always @(posedge clk) begin + if (write_enable == 1'b1) begin + registers[write_reg] <= write_data; + end + end + + always @(all) begin + read1_data <= registers[read1_reg]; + end +endmodule +EOT + +synth_ecp5 -abc9 diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys new file mode 100644 index 000000000..1d1682fcd --- /dev/null +++ b/tests/arch/ecp5/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 diff --git a/tests/arch/ecp5/bug1630.il.gz b/tests/arch/ecp5/bug1630.il.gz Binary files differnew file mode 100644 index 000000000..37bcf2be2 --- /dev/null +++ b/tests/arch/ecp5/bug1630.il.gz diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys new file mode 100644 index 000000000..b419fb9bb --- /dev/null +++ b/tests/arch/ecp5/bug1630.ys @@ -0,0 +1,2 @@ +read_ilang bug1630.il.gz +abc9 -lut +/ecp5/abc9_5g.lut diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index f9f60fbff..e46001ffe 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:CCU2C diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/lutram.ys index c82b7b405..e1ae7abd5 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 @@ -10,7 +10,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 24 t:L6MUX21 select -assert-count 71 t:LUT4 select -assert-count 32 t:PFUMX diff --git a/tests/arch/ecp5/macc.ys b/tests/arch/ecp5/macc.ys index 1863ea4d2..8da8d2f8e 100644 --- a/tests/arch/ecp5/macc.ys +++ b/tests/arch/ecp5/macc.ys @@ -3,8 +3,8 @@ hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +synth_ecp5 +#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys index 2105be52c..f887e9585 100644 --- a/tests/arch/ecp5/mul.ys +++ b/tests/arch/ecp5/mul.ys @@ -3,9 +3,9 @@ hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +synth_ecp5 -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:MULT18X18D select -assert-none t:MULT18X18D %% t:* %D diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 92463aa32..22866832d 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 8 t:L6MUX21 -select -assert-count 26 t:LUT4 -select -assert-count 12 t:PFUMX +select -assert-count 12 t:L6MUX21 +select -assert-count 34 t:LUT4 +select -assert-count 17 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys index d20b8ae27..f8fb29a87 100644 --- a/tests/arch/efinix/counter.ys +++ b/tests/arch/efinix/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -assert -multiclock -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/lutram.ys index 6f6acdcde..dcf647ce0 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix @@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_RAM_5K select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys index 920479d44..bdbc7ee24 100644 --- a/tests/arch/gowin/counter.ys +++ b/tests/arch/gowin/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/lutram.ys index 8f88cdd7c..56f69e7c5 100644 --- a/tests/arch/gowin/memory.ys +++ b/tests/arch/gowin/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin @@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:RAM16S4 # other logic present that is not simple #select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys new file mode 100644 index 000000000..8438cb979 --- /dev/null +++ b/tests/arch/ice40/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys new file mode 100644 index 000000000..27b6fb5e8 --- /dev/null +++ b/tests/arch/ice40/bug1626.ys @@ -0,0 +1,217 @@ +read_ilang <<EOT +# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os) +autoidx 2815 +attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9" +attribute \cells_not_processed 1 +attribute \dynports 1 +module \ahb_async_sram_halfwidth + parameter \DEPTH + parameter \W_ADDR + parameter \W_BYTEADDR + parameter \W_DATA + parameter \W_SRAM_ADDR + parameter \W_SRAM_DATA + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\addr_lsb[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\hready_r[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\long_dphase[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire width 16 $0\rdata_buf[15:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\read_dph[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\write_dph[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62" + wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55" + wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65" + wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50" + wire \addr_lsb + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24" + wire width 32 \ahbls_haddr + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28" + wire width 3 \ahbls_hburst + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30" + wire \ahbls_hmastlock + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29" + wire width 4 \ahbls_hprot + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32" + wire width 32 \ahbls_hrdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22" + wire \ahbls_hready + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21" + wire \ahbls_hready_resp + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23" + wire \ahbls_hresp + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27" + wire width 3 \ahbls_hsize + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26" + wire width 2 \ahbls_htrans + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31" + wire width 32 \ahbls_hwdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25" + wire \ahbls_hwrite + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire \aphase_full_width + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55" + wire width 2 \bytemask + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 \bytemask_noshift + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17" + wire \clk + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46" + wire \hready_r + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47" + wire \long_dphase + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64" + wire width 16 \rdata_buf + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49" + wire \read_dph + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18" + wire \rst_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34" + wire width 11 \sram_addr + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39" + wire width 2 \sram_byte_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36" + wire \sram_ce_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35" + wire width 16 \sram_dq + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38" + wire \sram_oe_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61" + wire width 16 \sram_q + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62" + wire width 16 \sram_rdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 16 \sram_wdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37" + wire \sram_we_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58" + wire \we_next + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48" + wire \write_dph + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436 + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" + switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y + case 1'1 + case + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78" + switch \ahbls_hready + case 1'1 + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79" + switch \ahbls_htrans [1] + case 1'1 + case + end + case + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y + case 1'1 + case + end + end + end + sync posedge \clk + sync negedge \rst_n + end + connect \ahbls_hresp 1'0 + connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y + connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y + connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y + connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y + connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y + connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y + connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y } + connect \ahbls_hready_resp \hready_r +end +EOT + +synth_ice40 -abc2 -abc9 diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz Binary files differnew file mode 100644 index 000000000..363c510ef --- /dev/null +++ b/tests/arch/ice40/bug1644.il.gz diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys new file mode 100644 index 000000000..5950f0e3c --- /dev/null +++ b/tests/arch/ice40/bug1644.ys @@ -0,0 +1,2 @@ +read_ilang bug1644.il.gz +synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index f112eb97d..7bbc4f2c3 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 6 t:SB_CARRY diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys new file mode 100644 index 000000000..250273859 --- /dev/null +++ b/tests/arch/ice40/ice40_dsp.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [15:0] a, b, output [31:0] o1, o2, o5); +SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1)); +assign o2 = a * 16'd0; +wire [31:0] o3, o4; +SB_MAC16 m2 (.A(a), .B(b), .O(o3)); +assign o4 = a * b; +SB_MAC16 m3 (.A(a), .B(b), .O(o5)); +endmodule +EOT +ice40_dsp diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index 5186d4800..011d98fef 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -1,24 +1,4 @@ read_verilog -icells -formal <<EOT -module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); - parameter LUT = 0; - SB_CARRY carry ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - \$lut #( - .WIDTH(4), - .LUT(LUT) - ) lut ( - .A({I0,A,B,I3}), - .Y(O) - ); -endmodule -EOT -design -stash unmap - -read_verilog -icells -formal <<EOT module top(input CI, I0, output [1:0] CO, output O); wire A = 1'b0, B = 1'b0; \$__ICE40_CARRY_WRAPPER #( @@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O); // A[1]: 1100 1100 1100 1100 // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 - .LUT(~16'b 0110_1001_1001_0110) + .LUT(~16'b 0110_1001_1001_0110), + .I3_IS_CI(1'b1) ) u0 ( .A(A), .B(B), .CI(CI), .I0(I0), - .I3(CI), + .I3(1'bx), .CO(CO[0]), .O(O) ); @@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O); endmodule EOT -equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt +equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt design -load postopt select -assert-count 1 t:* select -assert-count 1 t:$lut diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/lutram.ys index c356e67fb..1ba40f8ec 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 @@ -10,6 +10,6 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 9891b77d6..b8c3eb941 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog ../common/mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v index 0a0f41f37..71459fe38 100644 --- a/tests/arch/ice40/rom.v +++ b/tests/arch/ice40/rom.v @@ -2,7 +2,8 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. */ module top(data, addr); -output [3:0] data; +output [3:0] data; // Note: this prompts a Yosys warning, but + // vendor doc does not contain 'reg' input [4:0] addr; always @(addr) begin case (addr) diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys new file mode 100644 index 000000000..b457cefce --- /dev/null +++ b/tests/arch/xilinx/abc9_dff.ys @@ -0,0 +1,32 @@ +read_verilog <<EOT +module top(input C, D, output [7:0] Q); +FDRE fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0])); +FDSE fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1])); +FDCE fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2])); +FDPE fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3])); +FDRE_1 fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4])); +FDSE_1 fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5])); +FDCE_1 fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6])); +FDPE_1 fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7])); +endmodule +EOT +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* + +design -reset +read_verilog <<EOT +module top(input C, D, output [7:0] Q); +FDRE fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0])); +FDSE fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1])); +FDCE fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); +FDPE fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); +FDRE_1 fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4])); +FDSE_1 fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5])); +FDCE_1 fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); +FDPE_1 fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7])); +endmodule +EOT +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys new file mode 100644 index 000000000..4a7b9384a --- /dev/null +++ b/tests/arch/xilinx/abc9_map.ys @@ -0,0 +1,91 @@ +read_verilog <<EOT +module top(input C, CE, D, R, output [1:0] Q); +FDRE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[0])); +FDRE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[1])); +endmodule +EOT +design -save gold + +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE +techmap -map +/xilinx/abc9_unmap.v +select -assert-count 1 t:FDSE +select -assert-count 1 t:FDSE_1 +techmap -autoproc -map +/xilinx/cells_sim.v +design -stash gate + +design -import gold -as gold +design -import gate -as gate +techmap -autoproc -map +/xilinx/cells_sim.v + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 2 -verify -prove-asserts -show-ports miter + +design -reset +read_verilog <<EOT +module top(input C, CE, D, S, output [1:0] Q); +FDSE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[0])); +FDSE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[1])); +endmodule +EOT +design -save gold + +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE +techmap -map +/xilinx/abc9_unmap.v +select -assert-count 1 t:FDRE +select -assert-count 1 t:FDRE_1 +techmap -autoproc -map +/xilinx/cells_sim.v +design -stash gate + +design -import gold -as gold +design -import gate -as gate +techmap -autoproc -map +/xilinx/cells_sim.v + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter + +design -reset +read_verilog <<EOT +module top(input C, CE, D, PRE, output [1:0] Q); +FDPE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[0])); +FDPE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[1])); +endmodule +EOT +design -save gold + +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE +techmap -map +/xilinx/abc9_unmap.v +select -assert-count 1 t:FDCE +select -assert-count 1 t:FDCE_1 +techmap -autoproc -map +/xilinx/cells_sim.v +design -stash gate + +design -import gold -as gold +design -import gate -as gate +techmap -autoproc -map +/xilinx/cells_sim.v +clk2fflogic + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter + +design -reset +read_verilog <<EOT +module top(input C, CE, D, CLR, output [1:0] Q); +FDCE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[0])); +FDCE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[1])); +endmodule +EOT +design -save gold + +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE +techmap -map +/xilinx/abc9_unmap.v +select -assert-count 1 t:FDPE +techmap -autoproc -map +/xilinx/cells_sim.v +design -stash gate + +design -import gold -as gold +design -import gate -as gate +techmap -autoproc -map +/xilinx/cells_sim.v +clk2fflogic + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..70cfe81a3 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,11 +1,11 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 14 t:LUT2 -select -assert-count 6 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +stat +select -assert-count 16 t:LUT2 +select -assert-count 2 t:CARRY4 +select -assert-none t:LUT2 t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index e73bfe0b9..3328f9edc 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -28,24 +28,23 @@ select -assert-none t:BUFG t:FDCE t:INV %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 +select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDSE %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT2 +select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys new file mode 100644 index 000000000..7bdd94a63 --- /dev/null +++ b/tests/arch/xilinx/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram -noiopad +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram -noiopad +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual -noiopad +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual_syn -noiopad +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys new file mode 100644 index 000000000..ed743cf44 --- /dev/null +++ b/tests/arch/xilinx/blockram.ys @@ -0,0 +1,97 @@ +### TODO: Not running equivalence checking because BRAM models does not exists +### currently. Checking instance counts instead. +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + + +### With parameters + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set logic_block 1 m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory +synth_xilinx -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys new file mode 100644 index 000000000..09935ccd8 --- /dev/null +++ b/tests/arch/xilinx/bug1460.ys @@ -0,0 +1,34 @@ +read_verilog <<EOT +module register_file( + input wire clk, + input wire write_enable, + input wire [63:0] write_data, + input wire [4:0] write_reg, + input wire [4:0] read1_reg, + input wire [4:0] read2_reg, + input wire [4:0] read3_reg, + output reg [63:0] read1_data, + output reg [63:0] read2_data, + output reg [63:0] read3_data + ); + + reg [63:0] registers[0:31]; + + always @(posedge clk) begin + if (write_enable == 1'b1) begin + registers[write_reg] <= write_data; + end + end + + always @(all) begin + read1_data <= registers[read1_reg]; + read2_data <= registers[read2_reg]; + read3_data <= registers[read3_reg]; + end +endmodule +EOT + +synth_xilinx -noiopad +cd register_file +select -assert-count 32 t:RAM32M +select -assert-none t:* t:BUFG %d t:RAM32M %d diff --git a/tests/various/bug1462.ys b/tests/arch/xilinx/bug1462.ys index 15cab5121..15cab5121 100644 --- a/tests/various/bug1462.ys +++ b/tests/arch/xilinx/bug1462.ys diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys new file mode 100644 index 000000000..1175380b1 --- /dev/null +++ b/tests/arch/xilinx/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 diff --git a/tests/arch/xilinx/bug1605.ys b/tests/arch/xilinx/bug1605.ys new file mode 100644 index 000000000..4be659860 --- /dev/null +++ b/tests/arch/xilinx/bug1605.ys @@ -0,0 +1,19 @@ +read_verilog <<EOT +module top(inout io); + wire in; + wire t; + wire o; + + IOBUF IOBUF( + .I(in), + .T(t), + .IO(io), + .O(o) + ); +endmodule +EOT + +synth_xilinx +cd top +select -assert-count 1 t:IOBUF +select -assert-none t:* t:IOBUF %d diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 604acdbfc..064519ce7 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -2,13 +2,12 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 8 t:FDCE select -assert-count 1 t:INV -select -assert-count 7 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D +select -assert-count 2 t:CARRY4 +select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index 0bba4858f..dc764b033 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys new file mode 100644 index 000000000..ca6b619b9 --- /dev/null +++ b/tests/arch/xilinx/dsp_cascade.ys @@ -0,0 +1,89 @@ +design -reset +read_verilog <<EOT +module cascade(input clk, input [4:0] a, input [4:0] b, output reg [9:0] o); +reg [4:0] ar1, ar2, ar3, br1, br2, br3; +reg [9:0] m, n; +always @(posedge clk) begin +ar1 <= a; +ar2 <= ar1; +ar3 <= ar2; +br1 <= b; +br2 <= br1; +br3 <= br2; +m <= ar1 * br1; +n <= ar2 * br2 + m; +o <= ar3 * br3 + n; +end +endmodule +EOT +proc +design -save read + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad +design -load postopt +cd cascade +select -assert-count 3 t:DSP48E1 +select -assert-none t:DSP48E1 t:BUFG %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (i.e. Take all DSP48E1s, expand to find all wires connected +# to its PCOUT port, then remove all DSP48E1s from this +# selection, then expand again to find all cells where +# those wires are connected to the PCIN port, then remove +# all wires from this selection, and lastly intersect +# this selection with all DSP48E1 cells (to check that +# the connected cells are indeed DSPs) +select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i + +design -load read +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad +design -load postopt +cd cascade +select -assert-count 3 t:DSP48A1 +select -assert-count 5 t:FDRE # No cascade for A input +select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (see above for explanation) +select -assert-count 2 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i + +design -reset +read_verilog <<EOT +module cascade(input clk, input [4:0] a, input [4:0] b, output reg [9:0] o); +reg [4:0] ar1, ar2, ar3, br1, br2, br3; +reg [9:0] m; +always @(posedge clk) begin +ar1 <= a; +ar2 <= ar1; +ar3 <= ar2; +br1 <= b; +br2 <= br1; +br3 <= br2; +m <= ar2 * br2; +o <= ar3 * br3 + m; +end +endmodule +EOT +proc +design -save read + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad +design -load postopt +cd cascade +select -assert-count 2 t:DSP48E1 +select -assert-none t:DSP48E1 t:BUFG %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (see above for explanation) +select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i + +design -load read +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad +design -load postopt +cd cascade +select -assert-count 2 t:DSP48A1 +select -assert-count 10 t:FDRE # Cannot cascade because first 'm' DSP + # uses both B0REG and B1REG, whereas 'o' + # only requires 1 +select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (see above for explanation) +select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i + diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 0067a822b..57fe49bde 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -63,7 +63,7 @@ module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_re endmodule EOT -synth_xilinx +synth_xilinx -noiopad cd fastfir_dynamictaps select -assert-count 2 t:DSP48E1 select -assert-none t:* t:DSP48E1 %d t:BUFG %d diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 2a72c34e8..a464fcfdb 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -3,16 +3,17 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG -select -assert-count 5 t:FDRE -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT4 -select -assert-count 4 t:LUT6 -select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D +select -assert-count 4 t:FDRE +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT2 +select -assert-count 3 t:LUT5 +select -assert-count 1 t:LUT6 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index c87a8e38b..e226c2ec8 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top latchp proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D design -load read hierarchy -top latchn proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -26,7 +26,7 @@ select -assert-none t:LDCE t:INV %% t:* %D design -load read hierarchy -top latchsr proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index d5b5c1a37..61a9314cc 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys new file mode 100644 index 000000000..3f127a77e --- /dev/null +++ b/tests/arch/xilinx/lutram.ys @@ -0,0 +1,137 @@ +#read_verilog ../common/lutram.v +#hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +#proc +#memory -nomap +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +#memory +#opt -full +# +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter +# +#design -load postopt +#cd lutram_1w1r +#select -assert-count 1 t:BUFG +#select -assert-count 8 t:FDRE +#select -assert-count 8 t:RAM16X1D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM32X1D +select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 4 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r -chparam A_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 8 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 1 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 2 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 154a29848..58b97b646 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,6 @@ ../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc +../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v +vvp -N ./test_macc diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 6e884b35a..bf2b36320 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -3,8 +3,8 @@ design -save read hierarchy -top macc proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) @@ -17,15 +17,16 @@ select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read hierarchy -top macc2 proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module + select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 +select -assert-count 40 t:LUT3 select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys deleted file mode 100644 index da1ed0e49..000000000 --- a/tests/arch/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index d76814966..490846ff1 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -1,9 +1,21 @@ read_verilog ../common/mul.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:DSP48E1 select -assert-none t:DSP48E1 %% t:* %D + +design -reset + +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48A1 +select -assert-none t:DSP48A1 %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 62495b90c..980263cbd 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -2,10 +2,24 @@ read_verilog mul_unsigned.v hierarchy -top mul_unsigned proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D + +design -reset + +read_verilog mul_unsigned.v +hierarchy -top mul_unsigned +proc + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48A1 +select -assert-count 30 t:FDRE +select -assert-none t:DSP48A1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 821d0fab7..99817738d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -14,7 +14,7 @@ select -assert-none t:LUT3 %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT6 @@ -25,7 +25,7 @@ select -assert-none t:LUT6 %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -37,9 +37,11 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 +select -assert-min 5 t:LUT6 +select -assert-max 7 t:LUT6 +select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 %% t:* %D +select -assert-none t:LUT6 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 455437f18..3652319a0 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index 4697703ca..eaccab126 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -7,6 +7,7 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D +select -assert-count 2 t:IBUF +select -assert-count 1 t:INV +select -assert-count 1 t:OBUFT +select -assert-none t:IBUF t:INV t:OBUFT %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys new file mode 100644 index 000000000..dc036acfd --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -0,0 +1,216 @@ +read_verilog << EOT + +// FDRE, mergeable CE and R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, inversions. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDCE, mergeable CE. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT5 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDRSE, mergeable CE, S, R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2])); +LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3])); + +FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT6 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT4 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/arch/xilinx/xilinx_dffopt_blacklist.txt b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt new file mode 100644 index 000000000..6a31a0cd3 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt @@ -0,0 +1,13 @@ +lut0 +lut1 +lut2 +lut3 +ff +ff.D +ff.R +ff.S +ff.CE +ff.d +ff.r +ff.s +ff.ce diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys new file mode 100644 index 000000000..3b9f52930 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5); +DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1)); +assign o2 = a * 16'd0; +wire [42:0] o3, o4; +DSP48E1 m2 (.A(a), .B(b), .P(o3)); +assign o4 = a * b; +DSP48E1 m3 (.A(a), .B(b), .P(o5)); +endmodule +EOT +xilinx_dsp diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 9bd38fcb3..88d0553b9 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -7,11 +7,9 @@ module MyMem #( input Clk_i, input [AddrWidth-1:0] Addr_i, input [DataWidth-1:0] Data_i, - output [DataWidth-1:0] Data_o, + output reg [DataWidth-1:0] Data_o, input WR_i); - reg [DataWidth-1:0] Data_o; - localparam Size = 2**AddrWidth; (* mem2reg *) diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index de60619d1..e5837d480 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc_box_id=1 *) +(* abc9_box_id=1, whitebox *) module MUXF8(input I0, I1, S, output O); endmodule @@ -264,3 +264,46 @@ always @* if (en) q <= d; endmodule + +module abc9_test031(input clk1, clk2, d, output reg q1, q2); +always @(posedge clk1) q1 <= d; +always @(negedge clk2) q2 <= q1; +endmodule + +module abc9_test032(input clk, d, r, output reg q); +always @(posedge clk or posedge r) + if (r) q <= 1'b0; + else q <= d; +endmodule + +module abc9_test033(input clk, d, r, output reg q); +always @(negedge clk or posedge r) + if (r) q <= 1'b1; + else q <= d; +endmodule + +module abc9_test034(input clk, d, output reg q1, q2); +always @(posedge clk) q1 <= d; +always @(posedge clk) q2 <= q1; +endmodule + +module abc9_test035(input clk, d, output reg [1:0] q); +always @(posedge clk) q[0] <= d; +always @(negedge clk) q[1] <= q[0]; +endmodule + +module abc9_test036(input A, B, S, output [1:0] O); + (* keep *) + MUXF8 m ( + .I0(I0), + .I1(I1), + .O(O[0]), + .S(S) + ); + MUXF8 m2 ( + .I0(I0), + .I1(I1), + .O(O[1]), + .S(S) + ); +endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 0d4262005..32d7a80ca 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -20,10 +20,13 @@ fi cp ../simple/*.v . cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\ hierarchy; \ synth -run coarse; \ opt -full; \ - techmap; abc9 -lut 4 -box ../abc.box; \ + techmap; \ + abc9 -lut 4 -box ../abc.box; \ + clean; \ check -assert; \ - select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" + select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ + setattr -mod -unset whitebox'" diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys new file mode 100644 index 000000000..2140dde26 --- /dev/null +++ b/tests/techmap/abc9.ys @@ -0,0 +1,81 @@ +read_verilog <<EOT +`define N 256 +module top(input [`N-1:0] a, output o); +wire [`N-2:0] w; +assign w[0] = a[0] & a[1]; +genvar i; +generate for (i = 1; i < `N-1; i++) +assign w[i] = w[i-1] & a[i+1]; +endgenerate +assign o = w[`N-2]; +endmodule +EOT +simplemap +dump +design -save gold + +abc9 -lut 4 + +design -load gold +abc9 -lut 4 -fast + +design -load gold +scratchpad -copy abc9.script.default.area abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.default.fast abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow2 abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow3 abc9.script +abc9 -lut 4 + +design -reset +read_verilog <<EOT +module top(input a, b, output o); +(* keep *) wire w = a & b; +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 2 t:$lut + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +wire w; +(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b)); +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 1 t:$lut +select -assert-count 1 t:$_AND_ + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +assign o = ~(a & b); +endmodule +EOT +abc9 -lut 4 +clean +select -assert-count 1 t:$lut +select -assert-none t:$lut t:* %D diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index f4345e906..c058d1607 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -28,6 +28,20 @@ assign io = oe ? i : 1'bz; assign o2 = io; assign o3 = ~io; endmodule + +module f(output o, o2); +assign o = 1'bz; +endmodule + +module g(inout io, output o); +assign o = io; +endmodule + +module h(inout io, output o, input i); +assign io = i; +assign o = io; +endmodule + EOT opt_clean @@ -97,3 +111,12 @@ select -assert-count 1 @oeb %co %co @iob %i select -assert-count 1 @iob %co %co @o2b %i select -assert-count 1 @iob %co %co t:$_NOT_ %i select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i + +select -assert-count 2 f/t:obuft + +select -assert-count 1 g/t:obuf +select -assert-count 1 g/t:iobuf + +select -assert-count 1 h/t:ibuf +select -assert-count 1 h/t:iobuf +select -assert-count 1 h/t:obuf diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 30ebd4e26..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -9,3 +9,10 @@ wire w; unknown u(~i, w); unknown2 u2(w, o); endmodule + +module abc9_test032(input clk, d, r, output reg q); +initial q = 1'b0; +always @(negedge clk or negedge r) + if (!r) q <= 1'b0; + else q <= d; +endmodule diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 5c9a4075d..0c7695089 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -14,6 +14,7 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + design -load read hierarchy -top abc9_test028 proc @@ -22,3 +23,33 @@ abc9 -lut 4 select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D + + +design -load read +hierarchy -top abc9_test032 +proc +clk2fflogic +design -save gold + +abc9 -lut 4 +check +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 10 -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells <<EOT +module abc9_test036(input clk, d, output q); +(* keep *) reg w; +$__ABC9_FF_ ff(.D(d), .Q(w)); +wire \ff.clock = clk; +wire \ff.init = 1'b0; +assign q = w; +endmodule +EOT +abc9 -lut 4 -dff diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys new file mode 100644 index 000000000..830962e81 --- /dev/null +++ b/tests/various/autoname.ys @@ -0,0 +1,19 @@ +read_ilang <<EOT +autoidx 2 +module \top + wire output 3 $y + wire input 1 \a + wire input 2 \b + cell $and \b_$and_B + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $y + end +end +EOT +autoname diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys new file mode 100644 index 000000000..542223030 --- /dev/null +++ b/tests/various/bug1531.ys @@ -0,0 +1,34 @@ +read_verilog <<EOT +module top (y, clk, w); + output reg y = 1'b0; + input clk, w; + reg [1:0] i = 2'b00; + always @(posedge clk) + // If the constant below is set to 2'b00, the correct output is generated. + // vvvv + for (i = 1'b0; i < 2'b01; i = i + 2'b01) + y <= w || i[1:1]; +endmodule +EOT + +synth +design -stash gate + +read_verilog <<EOT +module gold (y, clk, w); + input clk; + wire [1:0] i; + input w; + output y; + reg y = 1'h0; + always @(posedge clk) + y <= w; + assign i = 2'h0; +endmodule +EOT +proc gold + +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 10 -verify -prove-asserts -show-ports miter diff --git a/tests/various/scratchpad.ys b/tests/various/scratchpad.ys new file mode 100644 index 000000000..dc94081ea --- /dev/null +++ b/tests/various/scratchpad.ys @@ -0,0 +1,5 @@ +scratchpad -set foo "bar baz" +scratchpad -copy foo oof +scratchpad -unset foo +scratchpad -assert oof "bar baz" +scratchpad -assert-unset foo |