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-rw-r--r--tests/aiger/.gitignore2
-rw-r--r--tests/rpc/frontend.py7
-rwxr-xr-xtests/rpc/run-test.sh1
-rw-r--r--tests/rpc/unix.ys6
-rw-r--r--tests/svtypes/enum_simple.sv47
-rw-r--r--tests/svtypes/enum_simple.ys5
-rw-r--r--tests/svtypes/typedef_package.sv3
-rw-r--r--tests/svtypes/typedef_scopes.sv14
-rw-r--r--tests/techmap/iopadmap.ys37
-rw-r--r--tests/various/bug1614.ys5
-rw-r--r--tests/various/specify.v29
-rw-r--r--tests/various/specify.ys21
12 files changed, 166 insertions, 11 deletions
diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore
index 9a26bb8f4..b76bdb653 100644
--- a/tests/aiger/.gitignore
+++ b/tests/aiger/.gitignore
@@ -1 +1,3 @@
/*_ref.v
+/*.aag.log
+/*.aig.log
diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py
index eff41738a..eace07bf9 100644
--- a/tests/rpc/frontend.py
+++ b/tests/rpc/frontend.py
@@ -31,7 +31,7 @@ end
import json
import argparse
-import sys, socket, os
+import sys, socket, os, subprocess
try:
import msvcrt, win32pipe, win32file
except ImportError:
@@ -85,6 +85,7 @@ def main():
sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
sock.bind(args.path)
try:
+ ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
sock.listen(1)
conn, addr = sock.accept()
file = conn.makefile("rw")
@@ -93,7 +94,11 @@ def main():
if not input: break
file.write(call(input) + "\n")
file.flush()
+ ys_proc.wait(timeout=10)
+ if ys_proc.returncode:
+ raise subprocess.CalledProcessError(ys_proc.returncode, ys_proc.args)
finally:
+ ys_proc.kill()
sock.close()
os.unlink(args.path)
diff --git a/tests/rpc/run-test.sh b/tests/rpc/run-test.sh
index 44ce7e674..eeb309347 100755
--- a/tests/rpc/run-test.sh
+++ b/tests/rpc/run-test.sh
@@ -4,3 +4,4 @@ for x in *.ys; do
echo "Running $x.."
../../yosys -ql ${x%.ys}.log $x
done
+python3 frontend.py unix-socket frontend.sock
diff --git a/tests/rpc/unix.ys b/tests/rpc/unix.ys
deleted file mode 100644
index cc7ec14ab..000000000
--- a/tests/rpc/unix.ys
+++ /dev/null
@@ -1,6 +0,0 @@
-!python3 frontend.py unix-socket frontend.sock & sleep 0.1
-connect_rpc -path frontend.sock
-read_verilog design.v
-hierarchy -top top
-flatten
-select -assert-count 1 t:$neg
diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv
new file mode 100644
index 000000000..ccaf50da0
--- /dev/null
+++ b/tests/svtypes/enum_simple.sv
@@ -0,0 +1,47 @@
+
+module enum_simple(input clk, input rst);
+
+ enum {s0, s1, s2, s3} test_enum;
+ typedef enum logic [1:0] {
+ ts0, ts1, ts2, ts3
+ } states_t;
+ (states_t) state;
+ (states_t) enum_const = ts1;
+
+ always @(posedge clk) begin
+ if (rst) begin
+ test_enum <= s3;
+ state <= ts0;
+ end else begin
+ //test_enum
+ if (test_enum == s0)
+ test_enum <= s1;
+ else if (test_enum == s1)
+ test_enum <= s2;
+ else if (test_enum == s2)
+ test_enum <= s3;
+ else if (test_enum == s3)
+ test_enum <= s0;
+ else
+ assert(1'b0); //should be unreachable
+
+ //state
+ if (state == ts0)
+ state <= ts1;
+ else if (state == ts1)
+ state <= ts2;
+ else if (state == ts2)
+ state <= ts0;
+ else
+ assert(1'b0); //should be unreachable
+ end
+ end
+
+ always @(*) begin
+ assert(state != 2'h3);
+ assert(s0 == '0);
+ assert(ts0 == '0);
+ assert(enum_const == ts1);
+ end
+
+endmodule
diff --git a/tests/svtypes/enum_simple.ys b/tests/svtypes/enum_simple.ys
new file mode 100644
index 000000000..79981657b
--- /dev/null
+++ b/tests/svtypes/enum_simple.ys
@@ -0,0 +1,5 @@
+
+read_verilog -sv enum_simple.sv
+hierarchy; proc; opt
+sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all
+
diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv
index a1e16d4b1..b766f10cf 100644
--- a/tests/svtypes/typedef_package.sv
+++ b/tests/svtypes/typedef_package.sv
@@ -1,11 +1,14 @@
package pkg;
typedef logic [7:0] uint8_t;
+ typedef enum logic [7:0] {bb=8'hBB} enum8_t;
endpackage
module top;
(* keep *) (pkg::uint8_t) a = 8'hAA;
+ (* keep *) (pkg::enum8_t) b_enum = pkg::bb;
always @* assert(a == 8'hAA);
+ always @* assert(b_enum == 8'hBB);
endmodule
diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
index faa385bd6..1c45c7057 100644
--- a/tests/svtypes/typedef_scopes.sv
+++ b/tests/svtypes/typedef_scopes.sv
@@ -1,23 +1,35 @@
typedef logic [3:0] outer_uint4_t;
+typedef enum logic {s0, s1} outer_enum_t;
module top;
(outer_uint4_t) u4_i = 8'hA5;
+ (outer_enum_t) enum4_i = s0;
always @(*) assert(u4_i == 4'h5);
+ always @(*) assert(enum4_i == 1'b0);
typedef logic [3:0] inner_type;
+ typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t;
(inner_type) inner_i1 = 8'h5A;
+ (inner_enum_t) inner_enum1 = s3;
always @(*) assert(inner_i1 == 4'hA);
+ always @(*) assert(inner_enum1 == 3'h3);
if (1) begin: genblock
typedef logic [7:0] inner_type;
- (inner_type) inner_gb_i = 8'hA5;
+ parameter (inner_type) inner_const = 8'hA5;
+ typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t;
+ (inner_type) inner_gb_i = inner_const; //8'hA5;
+ (inner_enum_t) inner_gb_enum1 = s7;
always @(*) assert(inner_gb_i == 8'hA5);
+ always @(*) assert(inner_gb_enum1 == 3'h7);
end
(inner_type) inner_i2 = 8'h42;
+ (inner_enum_t) inner_enum2 = s4;
always @(*) assert(inner_i2 == 4'h2);
+ always @(*) assert(inner_enum2 == 3'h4);
endmodule
diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys
index c058d1607..0bcc71cce 100644
--- a/tests/techmap/iopadmap.ys
+++ b/tests/techmap/iopadmap.ys
@@ -120,3 +120,40 @@ select -assert-count 1 g/t:iobuf
select -assert-count 1 h/t:ibuf
select -assert-count 1 h/t:iobuf
select -assert-count 1 h/t:obuf
+
+
+# Check that \init attributes get moved from output buffer
+# to buffer input
+design -reset
+read_verilog << EOT
+module obuf (input i, (* iopad_external_pin *) output o); endmodule
+module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
+module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
+module sub(input i, output o); endmodule
+
+module a(input i, (* init=1'b1 *) output o);
+sub s(.i(i), .o(o));
+endmodule
+
+module b(input [1:0] i, oe, (* init=2'b1x *) output [1:0] o);
+wire [1:0] w;
+sub s1(.i(i[0]), .o(w[0]));
+sub s2(.i(i[1]), .o(w[1]));
+assign o = oe ? w : 2'bz;
+endmodule
+
+module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2);
+assign io = oe ? i : 1'bz;
+assign {o1,o2} = {io,io};
+endmodule
+EOT
+opt_clean
+tribuf
+simplemap
+iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
+select -assert-count 1 a/c:s %co a/a:init=1'b1 %i
+select -assert-count 1 a/a:init
+select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i
+select -assert-count 1 b/a:init
+select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i
+select -assert-count 1 c/a:init
diff --git a/tests/various/bug1614.ys b/tests/various/bug1614.ys
new file mode 100644
index 000000000..6fbe84a4c
--- /dev/null
+++ b/tests/various/bug1614.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module testcase;
+ wire [3:0] #1 a = 4'b0000;
+endmodule
+EOT
diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5d44d78f7..c160d2ec4 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,11 +7,9 @@ module test (
if (EN) Q <= D;
specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
-`endif
endspecify
endmodule
@@ -37,3 +35,30 @@ specify
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
+
+module test3(input clk, input [1:0] d, output [1:0] q);
+specify
+ (posedge clk => (q +: d)) = (3,1);
+ (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
+
+module test4(input clk, d, output q);
+specify
+ $setup(d, posedge clk, 1:2:3);
+ $setuphold(d, posedge clk, 1:2:3, 4:5:6);
+endspecify
+endmodule
+
+module test5(input clk, d, e, output q);
+specify
+ $setup(d, posedge clk &&& e, 1:2:3);
+endspecify
+endmodule
+
+module test6(input clk, d, e, output q);
+specify
+ (d[0] *> q[0]) = (3,1);
+ (posedge clk[0] => (q[0] +: d[0])) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 00597e1e2..9d55b8eb5 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,23 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog -specify <<EOT
+(* blackbox *)
+module test7_sub(input i, output o);
+specify
+ (i => o) = 1;
+endspecify
+assign o = ~i;
+endmodule
+
+module test7(input i, output o);
+ wire w;
+ test7_sub unused(i, w);
+ test7_sub used(i, o);
+endmodule
+EOT
+hierarchy
+cd test7
+clean
+select -assert-count 1 c:used
+select -assert-none c:* c:used %d
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-09 04:26:05 +0000