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-rw-r--r--tests/xilinx_ug901/mult_unsigned.v33
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diff --git a/tests/xilinx_ug901/mult_unsigned.v b/tests/xilinx_ug901/mult_unsigned.v
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+// Unsigned 16x24-bit Multiplier
+// 1 latency stage on operands
+// 3 latency stage after the multiplication
+// File: multipliers2.v
+//
+module mult_unsigned (clk, A, B, RES);
+//Default parameters were changed because of slow test
+//parameter WIDTHA = 16;
+//parameter WIDTHB = 24;
+parameter WIDTHA = 8;
+parameter WIDTHB = 12;
+input clk;
+input [WIDTHA-1:0] A;
+input [WIDTHB-1:0] B;
+output [WIDTHA+WIDTHB-1:0] RES;
+
+reg [WIDTHA-1:0] rA;
+reg [WIDTHB-1:0] rB;
+reg [WIDTHA+WIDTHB-1:0] M [3:0];
+
+integer i;
+always @(posedge clk)
+ begin
+ rA <= A;
+ rB <= B;
+ M[0] <= rA * rB;
+ for (i = 0; i < 3; i = i+1)
+ M[i+1] <= M[i];
+ end
+
+assign RES = M[3];
+
+endmodule