9 files changed, 173 insertions, 0 deletions
diff --git a/tests/verilog/bug2493.ys b/tests/verilog/bug2493.ys
new file mode 100644
index 000000000..380d2a823
--- /dev/null
+++ b/tests/verilog/bug2493.ys
@@ -0,0 +1,12 @@
+logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1
+read_verilog <<EOT
+module top1;
+    wire x;
+    generate
+        if (1) begin
+            mod y();
+            assign x = y;
+        end
+    endgenerate
+endmodule
+EOT
diff --git a/tests/verilog/bug656.v b/tests/verilog/bug656.v
new file mode 100644
index 000000000..068d045fd
--- /dev/null
+++ b/tests/verilog/bug656.v
@@ -0,0 +1,21 @@
+module top #(
+	parameter WIDTH = 6
+) (
+	input [WIDTH-1:0] a_i,
+	input [WIDTH-1:0] b_i,
+	output [WIDTH-1:0] z_o
+);
+	genvar g;
+	generate
+		for (g = 0; g < WIDTH; g = g + 1) begin
+			if (g > 2) begin
+				wire tmp;
+				assign tmp = a_i[g] || b_i[g];
+				assign z_o[g] = tmp;
+			end
+			else begin
+				assign z_o[g] = a_i[g] && b_i[g];
+			end
+		end
+	endgenerate
+endmodule
diff --git a/tests/verilog/bug656.ys b/tests/verilog/bug656.ys
new file mode 100644
index 000000000..7f367341a
--- /dev/null
+++ b/tests/verilog/bug656.ys
@@ -0,0 +1,13 @@
+read_verilog bug656.v
+
+select -assert-count 1 top/a_i
+select -assert-count 1 top/b_i
+select -assert-count 1 top/z_o
+
+select -assert-none top/genblk1[0].genblk1.tmp
+select -assert-none top/genblk1[1].genblk1.tmp
+select -assert-none top/genblk1[2].genblk1.tmp
+
+select -assert-count 1 top/genblk1[3].genblk1.tmp
+select -assert-count 1 top/genblk1[4].genblk1.tmp
+select -assert-count 1 top/genblk1[5].genblk1.tmp
diff --git a/tests/verilog/genblk_case.v b/tests/verilog/genblk_case.v
new file mode 100644
index 000000000..081fb09d3
--- /dev/null
+++ b/tests/verilog/genblk_case.v
@@ -0,0 +1,26 @@
+module top;
+	parameter YES = 1;
+	generate
+		if (YES) wire y;
+		else wire n;
+
+		if (!YES) wire n;
+		else wire y;
+
+		case (YES)
+			1: wire y;
+			0: wire n;
+		endcase
+
+		case (!YES)
+			0: wire y;
+			1: wire n;
+		endcase
+
+		if (YES) wire y;
+		else wire n;
+
+		if (!YES) wire n;
+		else wire y;
+	endgenerate
+endmodule
diff --git a/tests/verilog/genblk_case.ys b/tests/verilog/genblk_case.ys
new file mode 100644
index 000000000..3c1bb51f9
--- /dev/null
+++ b/tests/verilog/genblk_case.ys
@@ -0,0 +1,15 @@
+read_verilog genblk_case.v
+
+select -assert-count 0 top/genblk1.n
+select -assert-count 0 top/genblk2.n
+select -assert-count 0 top/genblk3.n
+select -assert-count 0 top/genblk4.n
+select -assert-count 0 top/genblk5.n
+select -assert-count 0 top/genblk6.n
+
+select -assert-count 1 top/genblk1.y
+select -assert-count 1 top/genblk2.y
+select -assert-count 1 top/genblk3.y
+select -assert-count 1 top/genblk4.y
+select -assert-count 1 top/genblk5.y
+select -assert-count 1 top/genblk6.y
diff --git a/tests/verilog/hidden_decl.ys b/tests/verilog/hidden_decl.ys
new file mode 100644
index 000000000..aed7847dc
--- /dev/null
+++ b/tests/verilog/hidden_decl.ys
@@ -0,0 +1,11 @@
+logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1
+read_verilog <<EOT
+`default_nettype none
+module top1;
+    wire x;
+    generate
+        if (1) wire y;
+    endgenerate
+    assign x = y;
+endmodule
+EOT
diff --git a/tests/verilog/unnamed_block.ys b/tests/verilog/unnamed_block.ys
new file mode 100644
index 000000000..0f209a089
--- /dev/null
+++ b/tests/verilog/unnamed_block.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+    initial begin : blk
+        integer x;
+    end
+endmodule
+EOT
+
+delete
+
+read_verilog -sv <<EOT
+module top;
+    initial begin
+        integer x;
+    end
+endmodule
+EOT
+
+delete
+
+logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+    initial begin
+        integer x;
+    end
+endmodule
+EOT
diff --git a/tests/verilog/unnamed_genblk.sv b/tests/verilog/unnamed_genblk.sv
new file mode 100644
index 000000000..41828b1b0
--- /dev/null
+++ b/tests/verilog/unnamed_genblk.sv
@@ -0,0 +1,39 @@
+// This test is taken directly from Section 27.6 of IEEE 1800-2017
+
+module top;
+	parameter genblk2 = 0;
+	genvar i;
+
+	// The following generate block is implicitly named genblk1
+
+	if (genblk2) logic a; // top.genblk1.a
+	else logic b; // top.genblk1.b
+
+	// The following generate block is implicitly named genblk02
+	// as genblk2 is already a declared identifier
+
+	if (genblk2) logic a; // top.genblk02.a
+	else logic b; // top.genblk02.b
+
+	// The following generate block would have been named genblk3
+	// but is explicitly named g1
+
+	for (i = 0; i < 1; i = i + 1) begin : g1 // block name
+		// The following generate block is implicitly named genblk1
+		// as the first nested scope inside g1
+		if (1) logic a; // top.g1[0].genblk1.a
+	end
+
+	// The following generate block is implicitly named genblk4 since
+	// it belongs to the fourth generate construct in scope "top".
+	// The previous generate block would have been
+	// named genblk3 if it had not been explicitly named g1
+
+	for (i = 0; i < 1; i = i + 1)
+		// The following generate block is implicitly named genblk1
+		// as the first nested generate block in genblk4
+		if (1) logic a; // top.genblk4[0].genblk1.a
+
+	// The following generate block is implicitly named genblk5
+	if (1) logic a; // top.genblk5.a
+endmodule
diff --git a/tests/verilog/unnamed_genblk.ys b/tests/verilog/unnamed_genblk.ys
new file mode 100644
index 000000000..2b9aa9d69
--- /dev/null
+++ b/tests/verilog/unnamed_genblk.ys
@@ -0,0 +1,8 @@
+read_verilog -sv unnamed_genblk.sv
+select -assert-count 0 top/genblk1.a
+select -assert-count 1 top/genblk02.b
+select -assert-count 0 top/genblk1.a
+select -assert-count 1 top/genblk02.b
+select -assert-count 1 top/g1[0].genblk1.a
+select -assert-count 1 top/genblk4[0].genblk1.a
+select -assert-count 1 top/genblk5.a