diff options
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/bug1745.ys | 8 | ||||
| -rw-r--r-- | tests/various/bug1781.ys | 33 | ||||
| -rw-r--r-- | tests/various/constcomment.ys | 16 | ||||
| -rw-r--r-- | tests/various/exec.ys | 6 | ||||
| -rw-r--r-- | tests/various/ice40_mince_abc9.ys | 17 | ||||
| -rw-r--r-- | tests/various/logger_error.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_nowarning.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warn.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warning.ys | 6 | ||||
| -rw-r--r-- | tests/various/src.ys | 8 | ||||
| -rw-r--r-- | tests/various/sv_defines.ys | 33 | ||||
| -rw-r--r-- | tests/various/sv_defines_dup.ys | 5 | ||||
| -rw-r--r-- | tests/various/sv_defines_mismatch.ys | 5 | ||||
| -rw-r--r-- | tests/various/sv_defines_too_few.ys | 7 |
14 files changed, 162 insertions, 0 deletions
diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys new file mode 100644 index 000000000..2e5b8c2d4 --- /dev/null +++ b/tests/various/bug1745.ys @@ -0,0 +1,8 @@ +logger -expect error "syntax error, unexpected TOK_CONSTVAL" 1 +read_verilog <<EOT +module inverter(input a, output y); + + assign y = (a == 1'b0? 1'b1 : 1'b0); + +endmodule // inverter +EOT diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys new file mode 100644 index 000000000..60dcc0830 --- /dev/null +++ b/tests/various/bug1781.ys @@ -0,0 +1,33 @@ +read_verilog <<EOT + +module top(input clk, input rst); + +reg [1:0] state; + +always @(posedge clk, posedge rst) begin + if (rst) + state <= 0; + else + case (state) + 2'b00: state <= 2'b01; + 2'b01: state <= 2'b10; + 2'b10: state <= 2'b00; + endcase +end + +sub sub_i(.i(state == 0)); + +endmodule + + +(* blackbox, keep *) +module sub(input i); +endmodule + +EOT + +proc +fsm + +# Make sure there is a driver +select -assert-any t:sub %ci %a w:* %i %ci c:* %i diff --git a/tests/various/constcomment.ys b/tests/various/constcomment.ys new file mode 100644 index 000000000..f4f2e75d8 --- /dev/null +++ b/tests/various/constcomment.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top1; + localparam a = 8 /*foo*/ 'h ab; + localparam b = 8 'h /*foo*/ cd; + generate + if (a != 8'b10101011) $error("a incorrect!"); + if (b != 8'b11001101) $error("b incorrect!"); + endgenerate +endmodule +EOT +logger -expect error "syntax error, unexpected TOK_BASE" 1 +read_verilog <<EOT +module top2; + localparam a = 12'h4 /*foo*/'b0; +endmodule +EOT diff --git a/tests/various/exec.ys b/tests/various/exec.ys new file mode 100644 index 000000000..0eec00719 --- /dev/null +++ b/tests/various/exec.ys @@ -0,0 +1,6 @@ +exec -expect-return 0 -- exit 0 +exec -expect-return 27 -- exit 27 +exec -expect-stdout nana -expect-stdout api -not-expect-stdout giraffe -- echo "bananapie" + +logger -expect error "stdout did have a line" 1 +exec -not-expect-stdout giraffe -- echo "giraffe" diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/src.ys b/tests/various/src.ys new file mode 100644 index 000000000..89d6700ca --- /dev/null +++ b/tests/various/src.ys @@ -0,0 +1,8 @@ +logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1 +logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1 +read_verilog <<EOT +module top(input i, output o, p); +always @* o <= i; +always @* p = i; +endmodule +EOT diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys new file mode 100644 index 000000000..8e70ee0ee --- /dev/null +++ b/tests/various/sv_defines.ys @@ -0,0 +1,33 @@ +# Check that basic macro expansions do what you'd expect + +read_verilog <<EOT +`define empty_arglist() 123 +`define one_arg(x) 123+x +`define opt_arg(x = 1) 123+x +`define two_args(x, y = (1+23)) x+y +`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y + +module top; + localparam a = `empty_arglist(); + localparam b = `one_arg(10); + localparam c = `opt_arg(10); + localparam d = `opt_arg(); + localparam e = `two_args(1,2); + localparam f = `two_args(1); + localparam g = `nested_comma(1, 2); + localparam h = `nested_comma({31'b0, (1'b0)}); + localparam i = `nested_comma(, 1); + + generate + if (a != 123) $error("a bad"); + if (b != 133) $error("b bad"); + if (c != 133) $error("c bad"); + if (d != 124) $error("d bad"); + if (e != 3) $error("e bad"); + if (f != 25) $error("f bad"); + if (g != 3) $error("g bad"); + if (h != 3) $error("h bad"); + if (i != 2) $error("i bad"); + endgenerate +endmodule +EOT diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys new file mode 100644 index 000000000..38418ba8f --- /dev/null +++ b/tests/various/sv_defines_dup.ys @@ -0,0 +1,5 @@ +# Check for duplicate arguments +logger -expect error "Duplicate macro arguments with name `x'" 1 +read_verilog <<EOT +`define duplicate_arg(x, x) +EOT diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys new file mode 100644 index 000000000..ab6e899de --- /dev/null +++ b/tests/various/sv_defines_mismatch.ys @@ -0,0 +1,5 @@ +# Check that we spot mismatched brackets +logger -expect error "Mismatched brackets in macro argument: \[ and }." 1 +read_verilog <<EOT +`define foo(x=[1,2}) +EOT diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys new file mode 100644 index 000000000..295884809 --- /dev/null +++ b/tests/various/sv_defines_too_few.ys @@ -0,0 +1,7 @@ +# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no" +# arguments actually passes 1 empty argument). +logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1 +read_verilog <<EOT +`define foo(x=1, y) +`foo() +EOT |