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-rw-r--r--tests/various/bug1480.ys18
-rw-r--r--tests/various/bug1614.ys5
-rw-r--r--tests/various/bug1710.ys30
-rw-r--r--tests/various/pmux2shiftx.v2
-rw-r--r--tests/various/sformatf.ys12
-rw-r--r--tests/various/specify.v29
-rw-r--r--tests/various/specify.ys21
-rwxr-xr-xtests/various/sv_implicit_ports.sh124
8 files changed, 219 insertions, 22 deletions
diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys
deleted file mode 100644
index 84faea08a..000000000
--- a/tests/various/bug1480.ys
+++ /dev/null
@@ -1,18 +0,0 @@
-read_verilog << EOF
-module top(...);
-
-input signed [17:0] A;
-input signed [17:0] B;
-output X;
-output Y;
-
-wire [35:0] P;
-assign P = A * B;
-
-assign X = P[0];
-assign Y = P[35];
-
-endmodule
-EOF
-
-synth_xilinx
diff --git a/tests/various/bug1614.ys b/tests/various/bug1614.ys
new file mode 100644
index 000000000..6fbe84a4c
--- /dev/null
+++ b/tests/various/bug1614.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module testcase;
+ wire [3:0] #1 a = 4'b0000;
+endmodule
+EOT
diff --git a/tests/various/bug1710.ys b/tests/various/bug1710.ys
new file mode 100644
index 000000000..c2ecf3c90
--- /dev/null
+++ b/tests/various/bug1710.ys
@@ -0,0 +1,30 @@
+logger -werror "out of bounds"
+read_verilog <<EOT
+module Example;
+
+ parameter FLAG = 1;
+ wire [3:0] inp;
+
+ reg out1;
+ initial out1 = FLAG ? &inp[2:0] : &inp[4:0];
+
+ reg out2;
+ initial
+ if (FLAG)
+ out2 = &inp[2:0];
+ else
+ out2 = &inp[4:0];
+
+ wire out3;
+ assign out3 = FLAG ? &inp[2:0] : &inp[4:0];
+
+ wire out4;
+ generate
+ if (FLAG)
+ assign out4 = &inp[2:0];
+ else
+ assign out4 = &inp[4:0];
+ endgenerate
+
+endmodule
+EOT
diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v
index 563394080..c1994e92c 100644
--- a/tests/various/pmux2shiftx.v
+++ b/tests/various/pmux2shiftx.v
@@ -33,7 +33,7 @@ module pmux2shiftx_test (
end
endmodule
-module issue01135(input [7:0] i, output o);
+module issue01135(input [7:0] i, output reg o);
always @*
case (i[6:3])
4: o <= i[0];
diff --git a/tests/various/sformatf.ys b/tests/various/sformatf.ys
new file mode 100644
index 000000000..66d6b0dbe
--- /dev/null
+++ b/tests/various/sformatf.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+
+module top;
+ localparam a = $sformatf("0x%x", 8'h5A);
+ localparam b = $sformatf("%d", 4'b011);
+ generate
+ if (a != "0x5a") $error("a incorrect!");
+ if (b != "3") $error("b incorrect!");
+ endgenerate
+endmodule
+
+EOT
diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5d44d78f7..c160d2ec4 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,11 +7,9 @@ module test (
if (EN) Q <= D;
specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
-`endif
endspecify
endmodule
@@ -37,3 +35,30 @@ specify
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
+
+module test3(input clk, input [1:0] d, output [1:0] q);
+specify
+ (posedge clk => (q +: d)) = (3,1);
+ (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
+
+module test4(input clk, d, output q);
+specify
+ $setup(d, posedge clk, 1:2:3);
+ $setuphold(d, posedge clk, 1:2:3, 4:5:6);
+endspecify
+endmodule
+
+module test5(input clk, d, e, output q);
+specify
+ $setup(d, posedge clk &&& e, 1:2:3);
+endspecify
+endmodule
+
+module test6(input clk, d, e, output q);
+specify
+ (d[0] *> q[0]) = (3,1);
+ (posedge clk[0] => (q[0] +: d[0])) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 00597e1e2..9d55b8eb5 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,23 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog -specify <<EOT
+(* blackbox *)
+module test7_sub(input i, output o);
+specify
+ (i => o) = 1;
+endspecify
+assign o = ~i;
+endmodule
+
+module test7(input i, output o);
+ wire w;
+ test7_sub unused(i, w);
+ test7_sub used(i, o);
+endmodule
+EOT
+hierarchy
+cd test7
+clean
+select -assert-count 1 c:used
+select -assert-none c:* c:used %d
diff --git a/tests/various/sv_implicit_ports.sh b/tests/various/sv_implicit_ports.sh
new file mode 100755
index 000000000..9a01447f7
--- /dev/null
+++ b/tests/various/sv_implicit_ports.sh
@@ -0,0 +1,124 @@
+#!/bin/bash
+
+trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
+
+# Simple case
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+ assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ wire [7:0] b = 8'd42;
+ add add_i(.*);
+endmodule
+EOT
+
+# Generate block
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ generate
+ if (1) begin:ablock
+ wire [7:0] b = 8'd42;
+ add add_i(.*);
+ end
+ endgenerate
+endmodule
+EOT
+
+# Missing wire
+((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+ assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ add add_i(.*);
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
+
+# Incorrectly sized wire
+((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+ assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ wire [6:0] b = 6'd42;
+ add add_i(.*);
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
+
+# Defaults
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
+assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ add add_i(.*);
+endmodule
+EOT
+
+# Parameterised module
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
+assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ add #(.N(8)) add_i(.*);
+endmodule
+EOT
+
+# Parameterised blackbox module
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
+(* blackbox *)
+module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
+endmodule
+
+module top(input [7:0] a, b, output [7:0] q);
+ add #(.N(8)) add_i(.*);
+endmodule
+EOT
+
+# Parameterised blackbox module - incorrect width
+((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
+(* blackbox *)
+module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
+endmodule
+
+module top(input [7:0] a, b, output [7:0] q);
+ add #(.N(6)) add_i(.*);
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
+
+# Mixed implicit and explicit 1
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+ assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ add add_i(.b(8'd42), .*);
+endmodule
+EOT
+
+# Mixed implicit and explicit 2
+(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a, input [7:0] b, output [7:0] q);
+ assign q = a + b;
+endmodule
+
+module top(input [7:0] a, input [9:0] b, output [7:0] q);
+ add add_i(.b, .*);
+endmodule
+EOT
+) 2>&1 | grep -F "Warning: Resizing cell port top.add_i.b from 10 bits to 8 bits." > /dev/null
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 03:32:06 +0000