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-rw-r--r--tests/various/deminout_unused.ys14
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys
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+++ b/tests/various/deminout_unused.ys
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+read_verilog <<EOT
+module top(input clk, inout [7:0] x);
+
+reg [3:0] ctr;
+always @(posedge clk) ctr <= ctr + 1'b1;
+
+assign x[7:4] = ctr;
+endmodule
+EOT
+proc
+tribuf
+deminout
+select -assert-count 1 i:x o:x %i
+