diff options
Diffstat (limited to 'tests/techmap/mem_simple_4x1_map.v')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_map.v | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 820f89de4..762e2938e 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -1,10 +1,11 @@ -module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); +module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; parameter SIZE = 256; parameter OFFSET = 0; parameter ABITS = 8; parameter WIDTH = 8; + parameter signed INIT = 1'bx; parameter RD_PORTS = 1; parameter RD_CLK_ENABLE = 1'b1; @@ -16,6 +17,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter WR_CLK_POLARITY = 1'b1; input [RD_PORTS-1:0] RD_CLK; + input [RD_PORTS-1:0] RD_EN; input [RD_PORTS*ABITS-1:0] RD_ADDR; output reg [RD_PORTS*WIDTH-1:0] RD_DATA; @@ -29,6 +31,8 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter _TECHMAP_CONNMAP_RD_CLK_ = 0; parameter _TECHMAP_CONNMAP_WR_CLK_ = 0; + parameter _TECHMAP_CONSTVAL_RD_EN_ = 0; + parameter _TECHMAP_BITS_CONNMAP_ = 0; parameter _TECHMAP_CONNMAP_WR_EN_ = 0; @@ -37,10 +41,18 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); initial begin _TECHMAP_FAIL_ <= 0; + // no initialized memories + if (INIT !== 1'bx) + _TECHMAP_FAIL_ <= 1; + // only map cells with only one read and one write port if (RD_PORTS > 1 || WR_PORTS > 1) _TECHMAP_FAIL_ <= 1; + // read enable must be constant high + if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1) + _TECHMAP_FAIL_ <= 1; + // we expect positive read clock and non-transparent reads if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY) _TECHMAP_FAIL_ <= 1; |