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Diffstat (limited to 'tests/sat/initval.ys')
| -rw-r--r-- | tests/sat/initval.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 337aa9343..6cb68a8d3 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts design -reset read_verilog -icells <<EOT module top(input clk, i, output o, p); +(* init = 1'b0 *) +wire o; (* init = 1'bx *) wire p = o; $_DFF_P_ dff (.C(clk), .D(i), .Q(o)); |