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-rw-r--r--tests/opt/bug2221.ys16
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/opt/bug2221.ys b/tests/opt/bug2221.ys
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+++ b/tests/opt/bug2221.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module test (
+ input [1:0] a,
+ input [1:0] b,
+ output [5:0] y
+);
+
+wire [5:0] aa = {a, 4'h0};
+wire [5:0] bb = {b, 4'h0};
+
+assign y = aa * bb;
+
+endmodule
+EOT
+
+equiv_opt -assert opt_expr