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-rw-r--r--tests/ice40/mul_pow.ys7
1 files changed, 4 insertions, 3 deletions
diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys
index 486480506..2a6baa738 100644
--- a/tests/ice40/mul_pow.ys
+++ b/tests/ice40/mul_pow.ys
@@ -1,6 +1,7 @@
-equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
synth_ice40
-select -assert-count 15 t:SB_LUT4
+#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
+equiv_opt -map +/ice40/cells_sim.v synth_ice40
+design -load postopt
+select -assert-count 16 t:SB_LUT4
select -assert-count 4 t:SB_CARRY
select -assert-count 1 t:$pow
-write_verilog ./temp/mul_pow_synth.v