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-rw-r--r--tests/arch/machxo2/counter.ys10
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/machxo2/counter.ys b/tests/arch/machxo2/counter.ys
new file mode 100644
index 000000000..54ee80066
--- /dev/null
+++ b/tests/arch/machxo2/counter.ys
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+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 4 t:CCU2D
+select -assert-count 8 t:TRELLIS_FF
+select -assert-none t:CCU2D t:TRELLIS_FF %% t:* %D