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-rw-r--r--tests/arch/xilinx/memory.ys17
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys
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+++ b/tests/arch/xilinx/memory.ys
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+read_verilog ../common/memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-count 8 t:RAM64X1D
+select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D