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-rw-r--r--tests/arch/xilinx/bug1462.ys11
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diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys
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+++ b/tests/arch/xilinx/bug1462.ys
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+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx