aboutsummaryrefslogtreecommitdiffstats
path: root/tests/arch/common
diff options
context:
space:
mode:
Diffstat (limited to 'tests/arch/common')
-rw-r--r--tests/arch/common/add_sub.v12
-rw-r--r--tests/arch/common/adffs.v43
-rw-r--r--tests/arch/common/counter.v11
-rw-r--r--tests/arch/common/dffs.v13
-rw-r--r--tests/arch/common/fsm.v51
-rw-r--r--tests/arch/common/latches.v21
-rw-r--r--tests/arch/common/logic.v16
-rw-r--r--tests/arch/common/memory.v21
-rw-r--r--tests/arch/common/mul.v9
-rw-r--r--tests/arch/common/mux.v60
-rw-r--r--tests/arch/common/shifter.v11
-rw-r--r--tests/arch/common/tribuf.v8
12 files changed, 276 insertions, 0 deletions
diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v
new file mode 100644
index 000000000..77e5f5745
--- /dev/null
+++ b/tests/arch/common/add_sub.v
@@ -0,0 +1,12 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+);
+
+ assign A = x + y;
+ assign B = x - y;
+endmodule
diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
new file mode 100644
index 000000000..576bd81a6
--- /dev/null
+++ b/tests/arch/common/adffs.v
@@ -0,0 +1,43 @@
+module adff( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, posedge clr )
+ if ( clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module adffn( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, negedge clr )
+ if ( !clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module dffs( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( pre )
+ q <= 1'b1;
+ else
+ q <= d;
+endmodule
+
+module ndffnr( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( negedge clk )
+ if ( !clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
new file mode 100644
index 000000000..9746fd701
--- /dev/null
+++ b/tests/arch/common/counter.v
@@ -0,0 +1,11 @@
+module top ( out, clk, reset );
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset)
+ out <= 8'b0;
+ else
+ out <= out + 1;
+endmodule
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
new file mode 100644
index 000000000..636252d16
--- /dev/null
+++ b/tests/arch/common/dffs.v
@@ -0,0 +1,13 @@
+module dff ( input d, clk, output reg q );
+ always @( posedge clk )
+ q <= d;
+endmodule
+
+module dffe( input d, clk, en, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( en )
+ q <= d;
+endmodule
diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
new file mode 100644
index 000000000..9d3fbb64a
--- /dev/null
+++ b/tests/arch/common/fsm.v
@@ -0,0 +1,51 @@
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3;
+ parameter IDLE = 3'b001;
+ parameter GNT0 = 3'b010;
+ parameter GNT1 = 3'b100;
+ parameter GNT2 = 3'b101;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end
+ else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+endmodule
diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v
new file mode 100644
index 000000000..60b757103
--- /dev/null
+++ b/tests/arch/common/latches.v
@@ -0,0 +1,21 @@
+module latchp ( input d, clk, en, output reg q );
+ always @*
+ if ( en )
+ q <= d;
+endmodule
+
+module latchn ( input d, clk, en, output reg q );
+ always @*
+ if ( !en )
+ q <= d;
+endmodule
+
+module latchsr ( input d, clk, en, clr, pre, output reg q );
+ always @*
+ if ( clr )
+ q <= 1'b0;
+ else if ( pre )
+ q <= 1'b1;
+ else if ( en )
+ q <= d;
+endmodule
diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v
new file mode 100644
index 000000000..c17899fa0
--- /dev/null
+++ b/tests/arch/common/logic.v
@@ -0,0 +1,16 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+);
+ assign B1 = in[0] & in[1];
+ assign B2 = in[0] | in[1];
+ assign B3 = in[0] ~& in[1];
+ assign B4 = in[0] ~| in[1];
+ assign B5 = in[0] ^ in[1];
+ assign B6 = in[0] ~^ in[1];
+ assign B7 = ~in[0];
+ assign B8 = in[0];
+ assign B9 = in[0:1] && in [2:3];
+ assign B10 = in[0:1] || in [2:3];
+endmodule
diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v
new file mode 100644
index 000000000..cb7753f7b
--- /dev/null
+++ b/tests/arch/common/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+ input [7:0] data_a,
+ input [6:1] addr_a,
+ input we_a, clk,
+ output reg [7:0] q_a
+);
+ // Declare the RAM variable
+ reg [7:0] ram[63:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ begin
+ ram[addr_a] <= data_a;
+ q_a <= data_a;
+ end
+ q_a <= ram[addr_a];
+ end
+endmodule
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v
new file mode 100644
index 000000000..437a91cfc
--- /dev/null
+++ b/tests/arch/common/mul.v
@@ -0,0 +1,9 @@
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+);
+ assign A = x * y;
+endmodule
diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v
new file mode 100644
index 000000000..71c1ac7f2
--- /dev/null
+++ b/tests/arch/common/mux.v
@@ -0,0 +1,60 @@
+module mux2 (S,A,B,Y);
+ input S;
+ input A,B;
+ output reg Y;
+
+ always @(*)
+ Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+ input[1:0] S;
+ input[3:0] D;
+ output Y;
+
+ reg Y;
+ wire[1:0] S;
+ wire[3:0] D;
+
+ always @*
+ begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ endcase
+ end
+endmodule
+
+module mux8 ( S, D, Y );
+ input[2:0] S;
+ input[7:0] D;
+ output Y;
+
+ reg Y;
+ wire[2:0] S;
+ wire[7:0] D;
+
+ always @*
+ begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ 4 : Y = D[4];
+ 5 : Y = D[5];
+ 6 : Y = D[6];
+ 7 : Y = D[7];
+ endcase
+ end
+endmodule
+
+module mux16 (D, S, Y);
+ input [15:0] D;
+ input [3:0] S;
+ output Y;
+
+ assign Y = D[S];
+endmodule
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
new file mode 100644
index 000000000..cace3b588
--- /dev/null
+++ b/tests/arch/common/shifter.v
@@ -0,0 +1,11 @@
+module top(out, clk, in);
+ output [7:0] out;
+ input signed clk, in;
+ reg signed [7:0] out = 0;
+
+ always @(posedge clk)
+ begin
+ out <= out >> 1;
+ out[7] <= in;
+ end
+endmodule
diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v
new file mode 100644
index 000000000..e1d701611
--- /dev/null
+++ b/tests/arch/common/tribuf.v
@@ -0,0 +1,8 @@
+module tristate(en, i, o);
+ input en;
+ input i;
+ output reg o;
+
+ always @(en or i)
+ o <= (en)? i : 1'bZ;
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 12:26:09 +0000