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-rw-r--r--techlibs/xilinx/cells_map.v48
-rw-r--r--techlibs/xilinx/synth_xilinx.cc4
-rw-r--r--techlibs/xilinx/xc6s_ff_map.v24
-rw-r--r--techlibs/xilinx/xc7_ff_map.v24
4 files changed, 50 insertions, 50 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 801949d22..97f050f76 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -28,32 +28,32 @@ module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPL
(* techmap_celltype = "$_DFF_PN1_" *)
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFE_NN0" *)
-module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_PN0" *)
-module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_NN1" *)
-module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_PN1" *)
-module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_NN0P_" *)
+module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$_DFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_PN0P_" *)
+module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$_DFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_NN1P_" *)
+module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$_DFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_PN1P_" *)
+module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$_DFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFS_NN0_" *)
-module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_PN0_" *)
-module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_NN1_" *)
-module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_PN1_" *)
-module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_NN0_" *)
+module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$_SDFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_PN0_" *)
+module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$_SDFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_NN1_" *)
+module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$_SDFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_PN1_" *)
+module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$_SDFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFSE_NN0" *)
-module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_PN0" *)
-module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_NN1" *)
-module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_PN1" *)
-module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_NN0P_" *)
+module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$_SDFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_PN0P_" *)
+module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$_SDFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_NN1P_" *)
+module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$_SDFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_PN1P_" *)
+module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$_SDFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a0d6c279a..b66dc850d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -540,7 +540,7 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("fine")) {
- run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
if (help_mode)
run("muxcover <internal options> ('-widemux' only)");
else if (widemux > 0) {
@@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_ffs", "('-abc9' only)")) {
if (abc9 || help_mode) {
if (dff || help_mode)
- run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)");
+ run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "('-dff' only)");
run("techmap -map " + ff_map_file);
}
}
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
index c40f446e0..a1e4218b9 100644
--- a/techlibs/xilinx/xc6s_ff_map.v
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -111,7 +111,7 @@ endmodule
// Async reset, enable.
-module \$__DFFE_NP0 (input D, C, E, R, output Q);
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
@@ -120,7 +120,7 @@ module \$__DFFE_NP0 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
@@ -130,7 +130,7 @@ module \$__DFFE_PP0 (input D, C, E, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q);
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
@@ -139,7 +139,7 @@ module \$__DFFE_NP1 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q);
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
@@ -151,7 +151,7 @@ endmodule
// Sync reset.
-module \$__DFFS_NP0_ (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -160,7 +160,7 @@ module \$__DFFS_NP0_ (input D, C, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -170,7 +170,7 @@ module \$__DFFS_PP0_ (input D, C, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -179,7 +179,7 @@ module \$__DFFS_NP1_ (input D, C, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -191,7 +191,7 @@ endmodule
// Sync reset, enable.
-module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -200,7 +200,7 @@ module \$__DFFSE_NP0 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -210,7 +210,7 @@ module \$__DFFSE_PP0 (input D, C, E, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -219,7 +219,7 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
index 2bd874457..750e8f8eb 100644
--- a/techlibs/xilinx/xc7_ff_map.v
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -89,23 +89,23 @@ endmodule
// Async reset, enable.
-module \$__DFFE_NP0 (input D, C, E, R, output Q);
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q);
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q);
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -113,23 +113,23 @@ endmodule
// Sync reset.
-module \$__DFFS_NP0_ (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -137,23 +137,23 @@ endmodule
// Sync reset, enable.
-module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 12:22:49 +0000