diff options
Diffstat (limited to 'techlibs/xilinx/xc7_ff_map.v')
| -rw-r--r-- | techlibs/xilinx/xc7_ff_map.v | 94 |
1 files changed, 78 insertions, 16 deletions
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v index 32ca9f560..2bd874457 100644 --- a/techlibs/xilinx/xc7_ff_map.v +++ b/techlibs/xilinx/xc7_ff_map.v @@ -37,6 +37,8 @@ `ifndef _NO_FFS +// No reset. + module \$_DFF_N_ (input D, C, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); @@ -48,6 +50,8 @@ module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// No reset, enable. + module \$_DFFE_NP_ (input D, C, E, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); @@ -59,47 +63,103 @@ module \$_DFFE_PP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); +// Async reset. + +module \$_DFF_NP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP0_ (input D, C, R, output Q); +module \$_DFF_PP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); + +module \$_DFF_NP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); +module \$_DFF_PP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); +// Async reset, enable. + +module \$__DFFE_NP0 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); + +module \$__DFFE_NP1 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); +module \$__DFFE_PP1 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset. + +module \$__DFFS_NP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFS_NP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFSE_NP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches (no reset). module \$_DLATCH_N_ (input E, D, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -112,5 +172,7 @@ module \$_DLATCH_P_ (input E, D, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Latches with reset (TODO). + `endif |