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-rw-r--r--techlibs/xilinx/cells_xtra.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 561a61943..13dbc0e14 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -108,8 +108,8 @@ XC6S_CELLS = [
# Cell('FDRE'),
# Cell('FDSE'),
Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
- Cell('LDCE'),
- Cell('LDPE'),
+ # Cell('LDCE'),
+ # Cell('LDPE'),
Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
# Slice/CLB primitives.