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-rw-r--r--techlibs/machxo2/cells_sim.v2
-rw-r--r--techlibs/machxo2/synth_machxo2.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 06fbe2023..22b4fcf3c 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -26,7 +26,7 @@ module FACADE_FF #(
parameter SRMODE = "LSR_OVER_CE",
parameter REGSET = "SET"
) (
- input CLK, D, LSR, CE,
+ input CLK, DI, LSR, CE,
output reg Q
);
diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc
index 625d708cc..f126f9c32 100644
--- a/techlibs/machxo2/synth_machxo2.cc
+++ b/techlibs/machxo2/synth_machxo2.cc
@@ -35,7 +35,7 @@ struct SynthMachXO2Pass : public ScriptPass
log("\n");
log(" synth_machxo2 [options]\n");
log("\n");
- log("This command runs synthesis for ECP5 FPGAs.\n");
+ log("This command runs synthesis for MachXO2 FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");