diff options
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 5d4c78d74..bf9e746b8 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -164,6 +164,7 @@ struct SynthIntelALMPass : public ScriptPass { run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str())); // Misc and common cells run("read_verilog -lib +/intel/common/altpll_bb.v"); @@ -190,7 +191,6 @@ struct SynthIntelALMPass : public ScriptPass { if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)"); - run("techmap -map +/intel_alm/common/lutram_mlab_map.v", "(for Cyclone V / Cyclone 10GX)"); } if (check_label("map_ffram")) { @@ -235,8 +235,7 @@ struct SynthIntelALMPass : public ScriptPass { // to constant driver cells, which Quartus accepts. run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q"); // Rename from Yosys-internal MISTRAL_* cells to Quartus cells. - run("techmap -map +/intel_alm/common/quartus_rename.v"); - run(stringf("techmap -map +/intel_alm/%s/quartus_rename.v", family_opt.c_str())); + run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str())); } } |