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-rw-r--r--techlibs/ice40/abc9_hx.box24
-rw-r--r--techlibs/ice40/abc9_lp.box24
-rw-r--r--techlibs/ice40/abc9_model.v4
-rw-r--r--techlibs/ice40/abc9_u.box24
-rw-r--r--techlibs/ice40/arith_map.v7
-rw-r--r--techlibs/ice40/cells_map.v19
-rw-r--r--techlibs/ice40/cells_sim.v1
-rw-r--r--techlibs/ice40/ice40_ffinit.cc10
-rw-r--r--techlibs/ice40/ice40_opt.cc26
-rw-r--r--techlibs/ice40/synth_ice40.cc26
10 files changed, 97 insertions, 68 deletions
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box
index 3ea70bc91..31e743669 100644
--- a/techlibs/ice40/abc9_hx.box
+++ b/techlibs/ice40/abc9_hx.box
@@ -1,13 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-400 379 449 316 316
-259 231 - - 126
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+400 379 449 316 316 # O
+259 231 - - 126 # CO
diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box
index 473e92fe9..71986a67b 100644
--- a/techlibs/ice40/abc9_lp.box
+++ b/techlibs/ice40/abc9_lp.box
@@ -1,13 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-589 558 661 465 465
-675 609 - - 186
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+589 558 661 465 465 # O
+675 609 - - 186 # CO
diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
index 26cf6cc22..a5e5f4372 100644
--- a/techlibs/ice40/abc9_model.v
+++ b/techlibs/ice40/abc9_model.v
@@ -9,6 +9,8 @@ module \$__ICE40_CARRY_WRAPPER (
input I0, I3
);
parameter LUT = 0;
+ parameter I3_IS_CI = 0;
+ wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
@@ -21,7 +23,7 @@ module \$__ICE40_CARRY_WRAPPER (
.I0(I0),
.I1(A),
.I2(B),
- .I3(I3),
+ .I3(I3_OR_CI),
.O(O)
);
endmodule
diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box
index f00e247b8..3d4b93834 100644
--- a/techlibs/ice40/abc9_u.box
+++ b/techlibs/ice40/abc9_u.box
@@ -1,13 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-1231 1205 1285 874 874
-675 609 - - 278
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+1231 1205 1285 874 874 # O
+675 609 - - 278 # CO
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 26b24db9e..ed4140e44 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -49,13 +49,14 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
- .LUT(16'b 0110_1001_1001_0110)
- ) fadd (
+ .LUT(16'b 0110_1001_1001_0110),
+ .I3_IS_CI(1'b1)
+ ) carry (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.I0(1'b0),
- .I3(C[i]),
+ .I3(1'bx),
.CO(CO[i]),
.O(Y[i])
);
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 662423f0a..759549e30 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,22 +61,3 @@ module \$lut (A, Y);
endgenerate
endmodule
`endif
-
-`ifndef NO_ADDER
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
- parameter LUT = 0;
- SB_CARRY carry (
- .I0(A),
- .I1(B),
- .CI(CI),
- .CO(CO)
- );
- \$lut #(
- .WIDTH(4),
- .LUT(LUT)
- ) lut (
- .A({I0,A,B,I3}),
- .Y(O)
- );
-endmodule
-`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7d1b37fd6..50eab5dde 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1126,6 +1126,7 @@ module SB_SPRAM256KA (
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+ `ABC9_ARRIVAL_U(1821) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207
output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index 3089d8932..c098736e9 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -78,10 +78,12 @@ struct Ice40FfinitPass : public Pass {
continue;
if (initbits.count(bit)) {
- if (initbits.at(bit) != val)
- log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+ if (initbits.at(bit) != val) {
+ log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+ initbits.at(bit) = State::Sx;
+ }
continue;
}
@@ -114,6 +116,10 @@ struct Ice40FfinitPass : public Pass {
continue;
State val = initbits.at(bit_q);
+
+ if (val == State::Sx)
+ continue;
+
handled_initbits.insert(bit_q);
log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index ea56d3f4d..df10a2842 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -41,6 +41,11 @@ static void run_ice40_opts(Module *module)
for (auto cell : module->selected_cells())
{
+ if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER"))
+ continue;
+ if (cell->has_keep_attr())
+ continue;
+
if (cell->type == "\\SB_LUT4")
{
sb_lut_cells.push_back(cell);
@@ -112,12 +117,30 @@ static void run_ice40_opts(Module *module)
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+ auto it = cell->attributes.find(ID(SB_LUT4.name));
+ if (it != cell->attributes.end()) {
+ module->rename(cell, it->second.decode_string());
+ decltype(Cell::attributes) new_attr;
+ for (const auto &a : cell->attributes)
+ if (a.first.begins_with("\\SB_LUT4.\\"))
+ new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
+ else if (a.first == ID(src))
+ new_attr.insert(std::make_pair(a.first, a.second));
+ else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
+ continue;
+ else if (a.first.begins_with("\\SB_CARRY.\\"))
+ continue;
+ else
+ log_abort();
+ cell->attributes = std::move(new_attr);
+ }
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
- cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
+ auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
+ cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
@@ -126,6 +149,7 @@ static void run_ice40_opts(Module *module)
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\WIDTH", 4);
+ cell->unsetParam("\\I3_IS_CI");
}
continue;
}
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 901194b06..d92e40726 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -65,7 +65,7 @@ struct SynthIce40Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nocarry\n");
log(" do not use SB_CARRY cells in output netlist\n");
@@ -102,8 +102,8 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
}
- string top_opt, blif_file, edif_file, json_file, abc, device_opt;
- bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
+ string top_opt, blif_file, edif_file, json_file, device_opt;
+ bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9;
int min_ce_use;
void clear_flags() YS_OVERRIDE
@@ -122,7 +122,7 @@ struct SynthIce40Pass : public ScriptPass
noabc = false;
abc2 = false;
vpr = false;
- abc = "abc";
+ abc9 = false;
device_opt = "hx";
}
@@ -207,7 +207,7 @@ struct SynthIce40Pass : public ScriptPass
continue;
}
if (args[argidx] == "-abc9") {
- abc = "abc9";
+ abc9 = true;
continue;
}
if (args[argidx] == "-device" && argidx+1 < args.size()) {
@@ -223,7 +223,7 @@ struct SynthIce40Pass : public ScriptPass
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
- if (abc == "abc9" && retime)
+ if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
log_header(design, "Executing SYNTH_ICE40 pass.\n");
@@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass
run("opt_expr");
run("opt_clean");
if (help_mode || dsp) {
- run("memory_dff");
+ run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
+ run("wreduce t:$mul");
run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
@@ -316,7 +317,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
if (retime || help_mode)
- run(abc + " -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
run("ice40_opt");
}
@@ -340,7 +341,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("map_luts"))
{
if (abc2 || help_mode) {
- run(abc, " (only if -abc2)");
+ run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
@@ -349,7 +350,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
- if (abc == "abc9") {
+ if (abc9) {
run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")
@@ -358,11 +359,12 @@ struct SynthIce40Pass : public ScriptPass
wire_delay = 750;
else
wire_delay = 250;
- run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
}
else
- run(abc + " -dress -lut 4", "(skip if -noabc)");
+ run("abc -dress -lut 4", "(skip if -noabc)");
}
+ run("ice40_wrapcarry -unwrap");
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("clean");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-28 10:57:50 +0000