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-rw-r--r--techlibs/ice40/synth_ice40.cc5
1 files changed, 0 insertions, 5 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 5073ba917..ed7a16c08 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -350,11 +350,6 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
- run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
- run("wbflip @abc9_boxes");
- run("techmap -autoproc @abc9_boxes");
- run("aigmap @abc9_boxes");
- run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")