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-rw-r--r--techlibs/coolrunner2/Makefile.inc2
-rw-r--r--techlibs/coolrunner2/cells_counter_map.v161
-rw-r--r--techlibs/coolrunner2/coolrunner2_fixup.cc520
-rw-r--r--techlibs/coolrunner2/coolrunner2_sop.cc172
-rw-r--r--techlibs/coolrunner2/synth_coolrunner2.cc5
5 files changed, 734 insertions, 126 deletions
diff --git a/techlibs/coolrunner2/Makefile.inc b/techlibs/coolrunner2/Makefile.inc
index d62c9960c..7a680c4fd 100644
--- a/techlibs/coolrunner2/Makefile.inc
+++ b/techlibs/coolrunner2/Makefile.inc
@@ -1,8 +1,10 @@
OBJS += techlibs/coolrunner2/synth_coolrunner2.o
OBJS += techlibs/coolrunner2/coolrunner2_sop.o
+OBJS += techlibs/coolrunner2/coolrunner2_fixup.o
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
+$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_counter_map.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
diff --git a/techlibs/coolrunner2/cells_counter_map.v b/techlibs/coolrunner2/cells_counter_map.v
new file mode 100644
index 000000000..b474fa522
--- /dev/null
+++ b/techlibs/coolrunner2/cells_counter_map.v
@@ -0,0 +1,161 @@
+module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
+
+ input wire CE;
+ input wire CLK;
+ output wire OUT;
+ output wire[WIDTH-1:0] POUT;
+ input wire RST;
+ input wire UP;
+
+ parameter COUNT_TO = 1;
+ parameter RESET_MODE = "RISING";
+ parameter RESET_TO_MAX = 0;
+ parameter HAS_POUT = 0;
+ parameter HAS_CE = 0;
+ parameter WIDTH = 8;
+ parameter DIRECTION = "DOWN";
+
+ if (DIRECTION == "UP") begin
+ if (WIDTH < 2) begin
+ initial begin
+ $display("ERROR: \$__COUNT_ must be at least 2 bits wide (bug in extract_counter pass?).");
+ $finish;
+ end
+ end
+
+ // FIXME: Max width?
+
+ assign OUT = POUT == COUNT_TO;
+
+ if (HAS_CE) begin
+ genvar i;
+ for (i = 0; i < WIDTH; i++) begin: countbits
+ // each bit = (cur & !reset) ^ (all prev & !reset)
+ wire xor_to_mc_bitn;
+ FDCP #(
+ .INIT(0)
+ ) bitn_ff (
+ .C(CLK),
+ .CLR(0),
+ .D(xor_to_mc_bitn),
+ .PRE(0),
+ .Q(POUT[i])
+ );
+ wire orterm_to_xor_bitn;
+ wire pterm0_to_or_bitn;
+ wire pterm1_to_or_bitn;
+ MACROCELL_XOR #(
+ .INVERT_OUT(0)
+ ) bitn_xor (
+ .IN_ORTERM(orterm_to_xor_bitn),
+ .IN_PTC(pterm1_to_or_bitn),
+ .OUT(xor_to_mc_bitn)
+ );
+ ORTERM #(
+ .WIDTH(1)
+ ) bitn_or (
+ .IN(pterm0_to_or_bitn),
+ .OUT(orterm_to_xor_bitn)
+ );
+ ANDTERM #(
+ .COMP_INP(1),
+ .TRUE_INP(1)
+ ) bitn_pterm0 (
+ .IN(POUT[i]),
+ .IN_B(OUT),
+ .OUT(pterm0_to_or_bitn)
+ );
+ ANDTERM #(
+ .COMP_INP(1),
+ .TRUE_INP(i + 1)
+ ) bitn_pterm1 (
+ .IN({POUT[i-1:0], CE}),
+ .IN_B(OUT),
+ .OUT(pterm1_to_or_bitn)
+ );
+ end
+ end else begin
+ // Bit0 is special; toggle unless reset
+ // cur reset out
+ // 0 0 1
+ // 0 1 0
+ // 1 0 0
+ // 1 1 0
+ wire xor_to_mc_bit0;
+ FDCP #(
+ .INIT(0)
+ ) bit0_ff (
+ .C(CLK),
+ .CLR(0),
+ .D(xor_to_mc_bit0),
+ .PRE(0),
+ .Q(POUT[0])
+ );
+ wire pterm_to_xor_bit0;
+ MACROCELL_XOR #(
+ .INVERT_OUT(0)
+ ) bit0_xor (
+ .IN_PTC(pterm_to_xor_bit0),
+ .OUT(xor_to_mc_bit0)
+ );
+ ANDTERM #(
+ .COMP_INP(2),
+ .TRUE_INP(0)
+ ) bit0_pterm (
+ .IN(),
+ .IN_B({POUT[0], OUT}),
+ .OUT(pterm_to_xor_bit0)
+ );
+
+ genvar i;
+ for (i = 1; i < WIDTH; i++) begin: countbits
+ // each bit = (cur & !reset) ^ (all prev & !reset)
+ wire xor_to_mc_bitn;
+ FDCP #(
+ .INIT(0)
+ ) bitn_ff (
+ .C(CLK),
+ .CLR(0),
+ .D(xor_to_mc_bitn),
+ .PRE(0),
+ .Q(POUT[i])
+ );
+ wire orterm_to_xor_bitn;
+ wire pterm0_to_or_bitn;
+ wire pterm1_to_or_bitn;
+ MACROCELL_XOR #(
+ .INVERT_OUT(0)
+ ) bitn_xor (
+ .IN_ORTERM(orterm_to_xor_bitn),
+ .IN_PTC(pterm1_to_or_bitn),
+ .OUT(xor_to_mc_bitn)
+ );
+ ORTERM #(
+ .WIDTH(1)
+ ) bitn_or (
+ .IN(pterm0_to_or_bitn),
+ .OUT(orterm_to_xor_bitn)
+ );
+ ANDTERM #(
+ .COMP_INP(1),
+ .TRUE_INP(1)
+ ) bitn_pterm0 (
+ .IN(POUT[i]),
+ .IN_B(OUT),
+ .OUT(pterm0_to_or_bitn)
+ );
+ ANDTERM #(
+ .COMP_INP(1),
+ .TRUE_INP(i)
+ ) bitn_pterm1 (
+ .IN(POUT[i-1:0]),
+ .IN_B(OUT),
+ .OUT(pterm1_to_or_bitn)
+ );
+ end
+ end
+ end
+
+ // FIXME: down counters
+
+endmodule
diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc
new file mode 100644
index 000000000..a71a1227e
--- /dev/null
+++ b/techlibs/coolrunner2/coolrunner2_fixup.cc
@@ -0,0 +1,520 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 R. Ou <rqou@robertou.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cellname)
+{
+ RTLIL::Wire *outwire = nullptr;
+
+ if (inwire == SigBit(true))
+ {
+ // Constant 1
+ outwire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
+ "\\MACROCELL_XOR");
+ xor_cell->setParam("\\INVERT_OUT", true);
+ xor_cell->setPort("\\OUT", outwire);
+ }
+ else if (inwire == SigBit(false))
+ {
+ // Constant 0
+ outwire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
+ "\\MACROCELL_XOR");
+ xor_cell->setParam("\\INVERT_OUT", false);
+ xor_cell->setPort("\\OUT", outwire);
+ }
+ else if (inwire == SigBit(RTLIL::State::Sx))
+ {
+ // x; treat as 0
+ log_warning("While buffering, changing x to 0 into cell %s\n", cellname);
+ outwire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
+ "\\MACROCELL_XOR");
+ xor_cell->setParam("\\INVERT_OUT", false);
+ xor_cell->setPort("\\OUT", outwire);
+ }
+ else
+ {
+ auto inwire_name = inwire.wire->name.c_str();
+
+ outwire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF_XOR_OUT", inwire_name)));
+
+ auto and_to_xor_wire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
+
+ auto and_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
+ "\\ANDTERM");
+ and_cell->setParam("\\TRUE_INP", 1);
+ and_cell->setParam("\\COMP_INP", 0);
+ and_cell->setPort("\\OUT", and_to_xor_wire);
+ and_cell->setPort("\\IN", inwire);
+ and_cell->setPort("\\IN_B", SigSpec());
+
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
+ "\\MACROCELL_XOR");
+ xor_cell->setParam("\\INVERT_OUT", false);
+ xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
+ xor_cell->setPort("\\OUT", outwire);
+ }
+
+ return outwire;
+}
+
+RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
+{
+ auto inwire_name = inwire.wire->name.c_str();
+
+ auto outwire = module->addWire(
+ module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
+
+ auto and_cell = module->addCell(
+ module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
+ "\\ANDTERM");
+ and_cell->setParam("\\TRUE_INP", 1);
+ and_cell->setParam("\\COMP_INP", 0);
+ and_cell->setPort("\\OUT", outwire);
+ and_cell->setPort("\\IN", inwire);
+ and_cell->setPort("\\IN_B", SigSpec());
+
+ return outwire;
+}
+
+struct Coolrunner2FixupPass : public Pass {
+ Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
+ void help() YS_OVERRIDE
+ {
+ log("\n");
+ log(" coolrunner2_fixup [options] [selection]\n");
+ log("\n");
+ log("Insert necessary buffer cells for CoolRunner-II architecture.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n");
+ extra_args(args, 1, design);
+
+ for (auto module : design->selected_modules())
+ {
+ SigMap sigmap(module);
+
+ // Find all the FF outputs
+ pool<SigBit> sig_fed_by_ff;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+ "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ {
+ auto output = sigmap(cell->getPort("\\Q")[0]);
+ sig_fed_by_ff.insert(output);
+ }
+ }
+
+ // Find all the XOR outputs
+ pool<SigBit> sig_fed_by_xor;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\MACROCELL_XOR")
+ {
+ auto output = sigmap(cell->getPort("\\OUT")[0]);
+ sig_fed_by_xor.insert(output);
+ }
+ }
+
+ // Find all the input/inout outputs
+ pool<SigBit> sig_fed_by_io;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type.in("\\IBUF", "\\IOBUFE"))
+ {
+ if (cell->hasPort("\\O")) {
+ auto output = sigmap(cell->getPort("\\O")[0]);
+ sig_fed_by_io.insert(output);
+ }
+ }
+ }
+
+ // Find all the pterm outputs
+ pool<SigBit> sig_fed_by_pterm;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\ANDTERM")
+ {
+ auto output = sigmap(cell->getPort("\\OUT")[0]);
+ sig_fed_by_pterm.insert(output);
+ }
+ }
+
+ // Find all the bufg outputs
+ pool<SigBit> sig_fed_by_bufg;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\BUFG")
+ {
+ auto output = sigmap(cell->getPort("\\O")[0]);
+ sig_fed_by_bufg.insert(output);
+ }
+ }
+
+ // Find all the bufgsr outputs
+ pool<SigBit> sig_fed_by_bufgsr;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\BUFGSR")
+ {
+ auto output = sigmap(cell->getPort("\\O")[0]);
+ sig_fed_by_bufgsr.insert(output);
+ }
+ }
+
+ // Find all the bufgts outputs
+ pool<SigBit> sig_fed_by_bufgts;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\BUFGTS")
+ {
+ auto output = sigmap(cell->getPort("\\O")[0]);
+ sig_fed_by_bufgts.insert(output);
+ }
+ }
+
+ // This is used to fix the input -> FF -> output scenario
+ pool<SigBit> sig_fed_by_ibuf;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\IBUF")
+ {
+ auto output = sigmap(cell->getPort("\\O")[0]);
+ sig_fed_by_ibuf.insert(output);
+ }
+ }
+
+ // Find all of the sinks for each output from an IBUF
+ dict<SigBit, std::pair<int, RTLIL::Cell *>> ibuf_fanouts;
+ for (auto cell : module->selected_cells())
+ {
+ for (auto &conn : cell->connections())
+ {
+ if (cell->input(conn.first))
+ {
+ for (auto wire_in : sigmap(conn.second))
+ {
+ if (sig_fed_by_ibuf[wire_in])
+ {
+ auto existing_count = ibuf_fanouts[wire_in].first;
+ ibuf_fanouts[wire_in] =
+ std::pair<int, RTLIL::Cell *>(existing_count + 1, cell);
+ }
+ }
+ }
+ }
+ }
+
+ dict<SigBit, RTLIL::Cell *> ibuf_out_to_packed_reg_cell;
+ pool<SigBit> packed_reg_out;
+ for (auto x : ibuf_fanouts)
+ {
+ auto ibuf_out_wire = x.first;
+ auto fanout_count = x.second.first;
+ auto maybe_ff_cell = x.second.second;
+
+ // The register can be packed with the IBUF only if it's
+ // actually a register and it's the only fanout. Otherwise,
+ // the pad-to-zia path has to be used up and the register
+ // can't be packed with the ibuf.
+ if (fanout_count == 1 && maybe_ff_cell->type.in(
+ "\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+ "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ {
+ SigBit input;
+ if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
+ input = sigmap(maybe_ff_cell->getPort("\\T")[0]);
+ else
+ input = sigmap(maybe_ff_cell->getPort("\\D")[0]);
+ SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]);
+
+ if (input == ibuf_out_wire)
+ {
+ log("Found IBUF %s that can be packed with FF %s (type %s)\n",
+ ibuf_out_wire.wire->name.c_str(),
+ maybe_ff_cell->name.c_str(),
+ maybe_ff_cell->type.c_str());
+
+ ibuf_out_to_packed_reg_cell[ibuf_out_wire] = maybe_ff_cell;
+ packed_reg_out.insert(output);
+ }
+ }
+ }
+
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+ "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ {
+ // Buffering FF inputs. FF inputs can only come from either
+ // an IO pin or from an XOR. Otherwise AND/XOR cells need
+ // to be inserted.
+ SigBit input;
+ if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
+ input = sigmap(cell->getPort("\\T")[0]);
+ else
+ input = sigmap(cell->getPort("\\D")[0]);
+
+ // If the input wasn't an XOR nor an IO, then a buffer
+ // definitely needs to be added.
+ // Otherwise, if it is an IO, only leave unbuffered
+ // if we're being packed with the IO.
+ if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) ||
+ (sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell))
+ {
+ log("Buffering input to \"%s\"\n", cell->name.c_str());
+
+ auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
+
+ if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
+ cell->setPort("\\T", xor_to_ff_wire);
+ else
+ cell->setPort("\\D", xor_to_ff_wire);
+ }
+
+ // Buffering FF clocks. FF clocks can only come from either
+ // a pterm or a bufg. In some cases this will be handled
+ // in coolrunner2_sop (e.g. if clock is generated from
+ // AND-ing two signals) but not in all cases.
+ SigBit clock;
+ if (cell->type.in("\\LDCP", "\\LDCP_N"))
+ clock = sigmap(cell->getPort("\\G")[0]);
+ else
+ clock = sigmap(cell->getPort("\\C")[0]);
+
+ if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
+ {
+ log("Buffering clock to \"%s\"\n", cell->name.c_str());
+
+ auto pterm_to_ff_wire = makeptermbuffer(module, clock);
+
+ if (cell->type.in("\\LDCP", "\\LDCP_N"))
+ cell->setPort("\\G", pterm_to_ff_wire);
+ else
+ cell->setPort("\\C", pterm_to_ff_wire);
+ }
+
+ // Buffering FF set/reset. This can only come from either
+ // a pterm or a bufgsr.
+ SigBit set;
+ set = sigmap(cell->getPort("\\PRE")[0]);
+ if (set != SigBit(false))
+ {
+ if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
+ {
+ log("Buffering set to \"%s\"\n", cell->name.c_str());
+
+ auto pterm_to_ff_wire = makeptermbuffer(module, set);
+
+ cell->setPort("\\PRE", pterm_to_ff_wire);
+ }
+ }
+
+ SigBit reset;
+ reset = sigmap(cell->getPort("\\CLR")[0]);
+ if (reset != SigBit(false))
+ {
+ if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
+ {
+ log("Buffering reset to \"%s\"\n", cell->name.c_str());
+
+ auto pterm_to_ff_wire = makeptermbuffer(module, reset);
+
+ cell->setPort("\\CLR", pterm_to_ff_wire);
+ }
+ }
+
+ // Buffering FF clock enable
+ // FIXME: This doesn't fully fix PTC conflicts
+ // FIXME: Need to ensure constant enables are optimized out
+ if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ {
+ SigBit ce;
+ ce = sigmap(cell->getPort("\\CE")[0]);
+ if (!sig_fed_by_pterm[ce])
+ {
+ log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
+
+ auto pterm_to_ff_wire = makeptermbuffer(module, ce);
+
+ cell->setPort("\\CE", pterm_to_ff_wire);
+ }
+ }
+ }
+ }
+
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\IOBUFE")
+ {
+ // Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
+ SigBit input = sigmap(cell->getPort("\\I")[0]);
+
+ if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
+ packed_reg_out[input])
+ {
+ log("Buffering input to \"%s\"\n", cell->name.c_str());
+
+ auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
+
+ cell->setPort("\\I", xor_to_io_wire);
+ }
+
+ // Buffer IOBUFE enables. This can only be fed from a pterm
+ // or a bufgts.
+ if (cell->hasPort("\\E"))
+ {
+ SigBit oe;
+ oe = sigmap(cell->getPort("\\E")[0]);
+ if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
+ {
+ log("Buffering output enable to \"%s\"\n", cell->name.c_str());
+
+ auto pterm_to_oe_wire = makeptermbuffer(module, oe);
+
+ cell->setPort("\\E", pterm_to_oe_wire);
+ }
+ }
+ }
+ }
+
+ // Now we have to fix up some cases where shared logic can
+ // cause XORs to have multiple fanouts to something other than
+ // pterms (which is not ok)
+
+ // Find all the XOR outputs
+ dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\MACROCELL_XOR")
+ {
+ auto output = sigmap(cell->getPort("\\OUT")[0]);
+ xor_out_to_xor_cell[output] = cell;
+ }
+ }
+
+ // Find all of the sinks for each output from an XOR
+ pool<SigBit> xor_fanout_once;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\ANDTERM")
+ continue;
+
+ for (auto &conn : cell->connections())
+ {
+ if (cell->input(conn.first))
+ {
+ for (auto wire_in : sigmap(conn.second))
+ {
+ auto xor_cell = xor_out_to_xor_cell[wire_in];
+ if (xor_cell)
+ {
+ if (xor_fanout_once[wire_in])
+ {
+ log("Additional fanout found for %s into %s (type %s), duplicating\n",
+ xor_cell->name.c_str(),
+ cell->name.c_str(),
+ cell->type.c_str());
+
+ auto new_xor_cell = module->addCell(
+ module->uniquify(xor_cell->name), xor_cell);
+ auto new_wire = module->addWire(
+ module->uniquify(wire_in.wire->name));
+ new_xor_cell->setPort("\\OUT", new_wire);
+ cell->setPort(conn.first, new_wire);
+ }
+ xor_fanout_once.insert(wire_in);
+ }
+ }
+ }
+ }
+ }
+
+ // Do the same fanout fixing for OR terms. By doing this
+ // after doing XORs, both pieces will be duplicated when necessary.
+
+ // Find all the OR outputs
+ dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\ORTERM")
+ {
+ auto output = sigmap(cell->getPort("\\OUT")[0]);
+ or_out_to_or_cell[output] = cell;
+ }
+ }
+
+ // Find all of the sinks for each output from an OR
+ pool<SigBit> or_fanout_once;
+ for (auto cell : module->selected_cells())
+ {
+ for (auto &conn : cell->connections())
+ {
+ if (cell->input(conn.first))
+ {
+ for (auto wire_in : sigmap(conn.second))
+ {
+ auto or_cell = or_out_to_or_cell[wire_in];
+ if (or_cell)
+ {
+ if (or_fanout_once[wire_in])
+ {
+ log("Additional fanout found for %s into %s (type %s), duplicating\n",
+ or_cell->name.c_str(),
+ cell->name.c_str(),
+ cell->type.c_str());
+
+ auto new_or_cell = module->addCell(
+ module->uniquify(or_cell->name), or_cell);
+ auto new_wire = module->addWire(
+ module->uniquify(wire_in.wire->name));
+ new_or_cell->setPort("\\OUT", new_wire);
+ cell->setPort(conn.first, new_wire);
+ }
+ or_fanout_once.insert(wire_in);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+} Coolrunner2FixupPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index de0cbb29d..581477473 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -94,6 +94,8 @@ struct Coolrunner2SopPass : public Pass {
auto sop_width = cell->getParam("\\WIDTH").as_int();
auto sop_table = cell->getParam("\\TABLE");
+ auto sop_output_wire_name = sop_output.wire->name.c_str();
+
// Check for a $_NOT_ at the output
bool has_invert = false;
if (not_cells.count(sop_output))
@@ -108,20 +110,15 @@ struct Coolrunner2SopPass : public Pass {
}
// Check for special P-term usage
- bool is_special_pterm = false;
- bool special_pterm_can_invert = false;
- if (special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output))
- {
- is_special_pterm = true;
- if (!special_pterms_no_inv[sop_output].size())
- special_pterm_can_invert = true;
- }
+ bool is_special_pterm =
+ special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output);
// Construct AND cells
pool<SigBit> intermed_wires;
for (int i = 0; i < sop_depth; i++) {
// Wire for the output
- auto and_out = module->addWire(NEW_ID);
+ auto and_out = module->addWire(
+ module->uniquify(stringf("$xc2sop$%s_AND%d_OUT", sop_output_wire_name, i)));
intermed_wires.insert(and_out);
// Signals for the inputs
@@ -140,7 +137,9 @@ struct Coolrunner2SopPass : public Pass {
}
// Construct the cell
- auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
+ auto and_cell = module->addCell(
+ module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
+ "\\ANDTERM");
and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
and_cell->setPort("\\OUT", and_out);
@@ -151,7 +150,9 @@ struct Coolrunner2SopPass : public Pass {
if (sop_depth == 1)
{
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
- auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
+ "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
@@ -159,88 +160,61 @@ struct Coolrunner2SopPass : public Pass {
// Special P-term handling
if (is_special_pterm)
{
- if (!has_invert || special_pterm_can_invert)
+ // Can always connect the P-term directly if it's going
+ // into something invert-capable
+ for (auto x : special_pterms_inv[sop_output])
{
- // Can connect the P-term directly to the special term sinks
- for (auto x : special_pterms_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
- for (auto x : special_pterms_no_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
- }
+ std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
- if (has_invert)
- {
- if (special_pterm_can_invert)
+ // If this signal is indeed inverted, flip the cell polarity
+ if (has_invert)
{
- log_assert(special_pterms_no_inv[sop_output].size() == 0);
-
- for (auto x : special_pterms_inv[sop_output])
- {
- auto cell = std::get<0>(x);
- // Need to invert the polarity of the cell
- if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
- else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
- else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
- else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
- else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
- else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
- else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
- else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
- else log_assert(!"Internal error! Bad cell type!");
- }
+ auto cell = std::get<0>(x);
+ if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
+ else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
+ else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
+ else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
+ else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
+ else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
+ else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
+ else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
+ else log_assert(!"Internal error! Bad cell type!");
}
- else
- {
- // Need to construct a feed-through term
- auto feedthrough_out = module->addWire(NEW_ID);
- auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
- feedthrough_cell->setParam("\\TRUE_INP", 1);
- feedthrough_cell->setParam("\\COMP_INP", 0);
- feedthrough_cell->setPort("\\OUT", feedthrough_out);
- feedthrough_cell->setPort("\\IN", sop_output);
- feedthrough_cell->setPort("\\IN_B", SigSpec());
+ }
- for (auto x : special_pterms_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
- for (auto x : special_pterms_no_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
- }
+ // If it's going into something that's not invert-capable,
+ // connect it directly only if this signal isn't inverted
+ if (!has_invert)
+ {
+ for (auto x : special_pterms_no_inv[sop_output])
+ std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
}
+
+ // Otherwise, a feedthrough P-term has to be created. Leave that to happen
+ // in the coolrunner2_fixup pass.
}
}
else
{
// Wire from OR to XOR
- auto or_to_xor_wire = module->addWire(NEW_ID);
+ auto or_to_xor_wire = module->addWire(
+ module->uniquify(stringf("$xc2sop$%s_OR_OUT", sop_output_wire_name)));
// Construct the OR cell
- auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
+ auto or_cell = module->addCell(
+ module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
+ "\\ORTERM");
or_cell->setParam("\\WIDTH", sop_depth);
or_cell->setPort("\\IN", intermed_wires);
or_cell->setPort("\\OUT", or_to_xor_wire);
// Construct the XOR cell
- auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
+ auto xor_cell = module->addCell(
+ module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
+ "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);
-
- if (is_special_pterm)
- {
- // Need to construct a feed-through term
- auto feedthrough_out = module->addWire(NEW_ID);
- auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
- feedthrough_cell->setParam("\\TRUE_INP", 1);
- feedthrough_cell->setParam("\\COMP_INP", 0);
- feedthrough_cell->setPort("\\OUT", feedthrough_out);
- feedthrough_cell->setPort("\\IN", sop_output);
- feedthrough_cell->setPort("\\IN_B", SigSpec());
-
- for (auto x : special_pterms_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
- for (auto x : special_pterms_no_inv[sop_output])
- std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
- }
}
// Finally, remove the $sop cell
@@ -248,60 +222,6 @@ struct Coolrunner2SopPass : public Pass {
}
}
- // In some cases we can get a FF feeding straight into an FF. This is not possible, so we need to insert
- // some AND/XOR cells in the middle to make it actually work.
-
- // Find all the FF outputs
- pool<SigBit> sig_fed_by_ff;
- for (auto cell : module->selected_cells())
- {
- if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
- "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
- {
- auto output = sigmap(cell->getPort("\\Q")[0]);
- sig_fed_by_ff.insert(output);
- }
- }
-
- // Look at all the FF inputs
- for (auto cell : module->selected_cells())
- {
- if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
- "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
- {
- SigBit input;
- if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
- input = sigmap(cell->getPort("\\T")[0]);
- else
- input = sigmap(cell->getPort("\\D")[0]);
-
- if (sig_fed_by_ff[input])
- {
- printf("Buffering input to \"%s\"\n", cell->name.c_str());
-
- auto and_to_xor_wire = module->addWire(NEW_ID);
- auto xor_to_ff_wire = module->addWire(NEW_ID);
-
- auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
- and_cell->setParam("\\TRUE_INP", 1);
- and_cell->setParam("\\COMP_INP", 0);
- and_cell->setPort("\\OUT", and_to_xor_wire);
- and_cell->setPort("\\IN", input);
- and_cell->setPort("\\IN_B", SigSpec());
-
- auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", false);
- xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
- xor_cell->setPort("\\OUT", xor_to_ff_wire);
-
- if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
- cell->setPort("\\T", xor_to_ff_wire);
- else
- cell->setPort("\\D", xor_to_ff_wire);
- }
- }
- }
-
// Actually do the removal now that we aren't iterating
for (auto cell : cells_to_remove)
{
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 3bac8623d..d5eeaf547 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -143,6 +143,9 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("fine"))
{
+ run("extract_counter -dir up -allow_arst no");
+ run("techmap -map +/coolrunner2/cells_counter_map.v");
+ run("clean");
run("opt -fast -full");
run("techmap -map +/techmap.v -map +/coolrunner2/cells_latch.v");
run("opt -fast");
@@ -175,9 +178,11 @@ struct SynthCoolrunner2Pass : public ScriptPass
run("dffinit -ff LDCP Q INIT");
run("dffinit -ff LDCP_N Q INIT");
run("coolrunner2_sop");
+ run("clean");
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");
+ run("coolrunner2_fixup");
run("splitnets");
run("clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-12 10:42:25 +0000