aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/common
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/Makefile.inc2
-rw-r--r--techlibs/common/abc9_model.v10
-rw-r--r--techlibs/common/dummy.box1
-rw-r--r--techlibs/common/synth.cc19
-rw-r--r--techlibs/common/techmap.v103
5 files changed, 97 insertions, 38 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index a42f63128..d5e69a241 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -29,4 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
-$(eval $(call add_share_file,share,techlibs/common/dummy.box))
+$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v
new file mode 100644
index 000000000..c0c5dc2fd
--- /dev/null
+++ b/techlibs/common/abc9_model.v
@@ -0,0 +1,10 @@
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
+(* abc9_box *)
+module \$__ABC9_DELAY (input I, output O);
+ parameter DELAY = 0;
+ specify
+ (I => O) = DELAY;
+ endspecify
+endmodule
diff --git a/techlibs/common/dummy.box b/techlibs/common/dummy.box
deleted file mode 100644
index 0c18070a0..000000000
--- a/techlibs/common/dummy.box
+++ /dev/null
@@ -1 +0,0 @@
-(dummy) 1 0 0 0
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index a176357a7..e7a192c07 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
+ log(" -flowmap\n");
+ log(" use FlowMap LUT techmapping instead of ABC\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -85,7 +88,7 @@ struct SynthPass : public ScriptPass
}
string top_module, fsm_opts, memory_opts, abc;
- bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
+ bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap;
int lut;
void clear_flags() YS_OVERRIDE
@@ -101,6 +104,7 @@ struct SynthPass : public ScriptPass
nofsm = false;
noabc = false;
noshare = false;
+ flowmap = false;
abc = "abc";
}
@@ -167,6 +171,10 @@ struct SynthPass : public ScriptPass
abc = "abc9";
continue;
}
+ if (args[argidx] == "-flowmap") {
+ flowmap = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -176,6 +184,8 @@ struct SynthPass : public ScriptPass
if (abc == "abc9" && !lut)
log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
+ if (flowmap && !lut)
+ log_cmd_error("FlowMap is only supported for FPGA synthesis (using '-lut' option)\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();
@@ -240,15 +250,20 @@ struct SynthPass : public ScriptPass
{
run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
run("clean; opt_lut", " (if -noabc and -lut)");
+ run("flowmap -maxlut K", " (if -flowmap and -lut)");
}
else if (noabc && lut)
{
run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
run("clean; opt_lut");
}
+ else if (flowmap)
+ {
+ run(stringf("flowmap -maxlut %d", lut));
+ }
run("opt -fast");
- if (!noabc) {
+ if (!noabc && !flowmap) {
#ifdef YOSYS_ENABLE_ABC
if (help_mode)
{
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index d7ec3947e..ecf4d5dc5 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -129,47 +129,82 @@ module _90_shift_shiftx (A, B, Y);
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
- localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
- localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
-
parameter _TECHMAP_CELLTYPE_ = "";
+ parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+ parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
- wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
- wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
+ generate
+`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
+ // If $shift/$shiftx only shifts in units of Y_WIDTH
+ // (a common pattern created by pmux2shiftx)
+ // which is checked by ensuring that all that
+ // the appropriate LSBs of B are constant zero,
+ // then we can decompose LSB first instead of
+ // MSB first
+ localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
+ if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
+ _TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
+ _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
+ // Halve the size of $shift/$shiftx by $mux-ing A according to
+ // the LSB of B, after discarding the zeroed bits
+ localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
+ localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
+ localparam len = Y_WIDTH2 * ((entries+1)/2);
+ wire [len-1:0] AA;
+ wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A};
+ genvar i;
+ for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
+ assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
+ wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
+ if (_TECHMAP_CELLTYPE_ == "$shift")
+ $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
+ else
+ $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
+ end
+ else
+`endif
+ begin
+ localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
+ localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
- integer i;
- reg [WIDTH-1:0] buffer;
- reg overflow;
+ wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
+ wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
- always @* begin
- overflow = 0;
- buffer = {WIDTH{extbit}};
- buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
-
- if (B_WIDTH > BB_WIDTH) begin
- if (B_SIGNED) begin
- for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
- if (B[i] != B[BB_WIDTH-1])
- overflow = 1;
- end else
- overflow = |B[B_WIDTH-1:BB_WIDTH];
- if (overflow)
- buffer = {WIDTH{extbit}};
- end
+ integer i;
+ reg [WIDTH-1:0] buffer;
+ reg overflow;
- for (i = BB_WIDTH-1; i >= 0; i = i-1)
- if (B[i]) begin
- if (B_SIGNED && i == BB_WIDTH-1)
- buffer = {buffer, {2**i{extbit}}};
- else if (2**i < WIDTH)
- buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
- else
- buffer = {WIDTH{extbit}};
+ always @* begin
+ overflow = 0;
+ buffer = {WIDTH{extbit}};
+ buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
+
+ if (B_WIDTH > BB_WIDTH) begin
+ if (B_SIGNED) begin
+ for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
+ if (B[i] != B[BB_WIDTH-1])
+ overflow = 1;
+ end else
+ overflow = |B[B_WIDTH-1:BB_WIDTH];
+ if (overflow)
+ buffer = {WIDTH{extbit}};
+ end
+
+ for (i = BB_WIDTH-1; i >= 0; i = i-1)
+ if (B[i]) begin
+ if (B_SIGNED && i == BB_WIDTH-1)
+ buffer = {buffer, {2**i{extbit}}};
+ else if (2**i < WIDTH)
+ buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
+ else
+ buffer = {WIDTH{extbit}};
+ end
end
- end
-
- assign Y = buffer;
+ assign Y = buffer;
+ end
+ endgenerate
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 19:16:20 +0000