1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 00f90bd4a..493292582 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1229,6 +1229,34 @@ endmodule
 `endif
 // --------------------------------------------------------
 
+module \$sop (A, Y);
+
+parameter WIDTH = 0;
+parameter DEPTH = 0;
+parameter TABLE = 0;
+
+input [WIDTH-1:0] A;
+output reg Y;
+
+integer i, j;
+reg match;
+
+always @* begin
+	Y = 0;
+	for (i = 0; i < DEPTH; i=i+1) begin
+		match = 1;
+		for (j = 0; j < WIDTH; j=j+1) begin
+			if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
+			if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
+		end
+		if (match) Y = 1;
+	end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$tribuf (A, EN, Y);
 
 parameter WIDTH = 0;