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-rw-r--r--techlibs/anlogic/synth_anlogic.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 3a1992588..aaa6bda4a 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -58,7 +58,7 @@ struct SynthAnlogicPass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nolutram\n");
log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
@@ -176,7 +176,7 @@ struct SynthAnlogicPass : public ScriptPass
{
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))