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-rwxr-xr-xtechlibs/achronix/Makefile.inc6
-rwxr-xr-xtechlibs/achronix/speedster22i/cells_arith.v (renamed from techlibs/achronix/speedster22i/cells_arith_speedster.v)8
-rwxr-xr-xtechlibs/achronix/speedster22i/cells_comb_speedster.v127
-rwxr-xr-xtechlibs/achronix/speedster22i/cells_map.v72
-rwxr-xr-xtechlibs/achronix/speedster22i/cells_map_speedster.v88
-rwxr-xr-xtechlibs/achronix/speedster22i/cells_sim.v80
-rwxr-xr-xtechlibs/achronix/synth_achronix.cc (renamed from techlibs/achronix/synth_speedster.cc)42
7 files changed, 180 insertions, 243 deletions
diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
index 4dfa59856..994cf0015 100755
--- a/techlibs/achronix/Makefile.inc
+++ b/techlibs/achronix/Makefile.inc
@@ -1,6 +1,6 @@
-OBJS += techlibs/achronix/synth_speedster.o
+OBJS += techlibs/achronix/synth_achronix.o
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v))
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
diff --git a/techlibs/achronix/speedster22i/cells_arith_speedster.v b/techlibs/achronix/speedster22i/cells_arith.v
index 9ef073f7c..e2194cbd7 100755
--- a/techlibs/achronix/speedster22i/cells_arith_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_arith.v
@@ -45,10 +45,10 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
-
+
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
+
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
@@ -61,5 +61,5 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
endgenerate
/* End implementation */
assign X = AA ^ BB;
-
-endmodule
+
+endmodule
diff --git a/techlibs/achronix/speedster22i/cells_comb_speedster.v b/techlibs/achronix/speedster22i/cells_comb_speedster.v
deleted file mode 100755
index 24c57c41a..000000000
--- a/techlibs/achronix/speedster22i/cells_comb_speedster.v
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-module VCC (output V);
- assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
- assign G = 1'b0;
-endmodule // GND
-
-/* Altera MAX10 devices Input Buffer Primitive */
-module PADIN (output padout, input padin);
- assign padout = padin;
-endmodule // fiftyfivenm_io_ibuf
-
-/* Altera MAX10 devices Output Buffer Primitive */
-module PADOUT (output padout, input padin, input oe);
- assign padout = padin;
- assign oe = oe;
-endmodule // fiftyfivenm_io_obuf
-
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
-module LUT4 (output dout,
- input din0, din1, din2, din3);
-
-/* Internal parameters which define the behaviour
- of the LUT primitive.
- lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
- dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
-parameter lut_function = 16'hFFFF;
-//parameter dont_touch = "off";
-//parameter lpm_type = "fiftyfivenm_lcell_comb";
-//parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
-reg cout_rt;
-reg combout_rt;
-wire dataa_w;
-wire datab_w;
-wire datac_w;
-wire datad_w;
-wire cin_w;
-
-assign dataa_w = din0;
-assign datab_w = din1;
-assign datac_w = din2;
-assign datad_w = din3;
-
-function lut_data;
-input [15:0] mask;
-input dataa, datab, datac, datad;
-reg [7:0] s3;
-reg [3:0] s2;
-reg [1:0] s1;
- begin
- s3 = datad ? mask[15:8] : mask[7:0];
- s2 = datac ? s3[7:4] : s3[3:0];
- s1 = datab ? s2[3:2] : s2[1:0];
- lut_data = dataa ? s1[1] : s1[0];
- end
-
-endfunction
-
-initial begin
- /*if (sum_lutc_input == "datac")*/ lut_type = 0;
- /*else
- if (sum_lutc_input == "cin") lut_type = 1;
- else begin
- $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
- $finish();
- end*/
-end
-
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
- if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_function, dataa_w, datab_w,
- datac_w, datad_w);
- end
- else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_function, dataa_w, datab_w,
- cin_w, datad_w);
- end
- cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
-end
-
-assign dout = combout_rt & 1'b1;
-//assign cout = cout_rt & 1'b1;
-
-endmodule // fiftyfivenm_lcell_comb
-
-/* Altera MAX10 D Flip-Flop Primitive */
-// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
- input asdata, aload, sclr, sload );
-
-parameter power_up="dontcare";
-parameter is_wysiwyg="false";
- reg q;
-
- always @(posedge clk)
- q <= d;
-
-endmodule
-
-
-
diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
new file mode 100755
index 000000000..9f647cbef
--- /dev/null
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -0,0 +1,72 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+
+// > Input/Output buffers <
+// Input buffer map
+module \$__inpad (input I, output O);
+ PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
+endmodule
+// Output buffer map
+module \$__outpad (input I, output O);
+ PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
+endmodule
+// > end buffers <
+
+// > Look-Up table <
+// > VT: I still think Achronix folks would have chosen a better \
+// > logic architecture.
+// LUT Map
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+ input [WIDTH-1:0] A;
+ output Y;
+ generate
+ if (WIDTH == 1) begin
+ // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
+ LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
+ end else
+ if (WIDTH == 2) begin
+ LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
+ end else
+ if(WIDTH == 3) begin
+ LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
+ end else
+ if(WIDTH == 4) begin
+ LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
+ end else
+ wire _TECHMAP_FAIL_ = 1;
+ endgenerate
+endmodule
+// > end LUT <
+
+// > Flops <
+// DFF flop
+module \$_DFF_P_ (input D, C, output Q);
+ DFF _TECHMAP_REPLACE_
+ (.q(Q), .d(D), .ck(C));
+endmodule
+
diff --git a/techlibs/achronix/speedster22i/cells_map_speedster.v b/techlibs/achronix/speedster22i/cells_map_speedster.v
deleted file mode 100755
index fb26eabf0..000000000
--- a/techlibs/achronix/speedster22i/cells_map_speedster.v
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-// Normal mode DFF negedge clk, negedge reset
-module \$_DFF_N_ (input D, C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Normal mode DFF
-module \$_DFF_P_ (input D, C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-
-// Async Active Low Reset DFF
-module \$_DFF_PN0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active High Reset DFF
-module \$_DFF_PP0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active Low Reset DFF
-module \$_DFF_PN0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-/* */
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
- parameter WYSIWYG="TRUE";
- wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
-endmodule
-
-// Input buffer map
-module \$__inpad (input I, output O);
- PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
- PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-/* 0 -> datac
- 1 -> cin */
-module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
- input [WIDTH-1:0] A;
- output Y;
- generate
- if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end else
- if (WIDTH == 2) begin
- LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
- end else
- if(WIDTH == 3) begin
- LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
- end else
- if(WIDTH == 4) begin
- LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
- end else
- wire _TECHMAP_FAIL_ = 1;
- endgenerate
-endmodule //
-
-
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
new file mode 100755
index 000000000..a0c60b4be
--- /dev/null
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -0,0 +1,80 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology sim models. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+// > Changelog: 1) Removed unused VCC/GND modules
+// > 2) Altera comments here (?). Removed.
+// > 3) Reusing LUT sim model, removed wrong wires and parameters.
+
+module PADIN (output padout, input padin);
+ assign padout = padin;
+endmodule
+
+module PADOUT (output padout, input padin, input oe);
+ assign padout = padin;
+ assign oe = oe;
+endmodule
+
+module LUT4 (output dout,
+ input din0, din1, din2, din3);
+
+parameter [15:0] lut_function = 16'hFFFF;
+reg combout_rt;
+wire dataa_w;
+wire datab_w;
+wire datac_w;
+wire datad_w;
+
+assign dataa_w = din0;
+assign datab_w = din1;
+assign datac_w = din2;
+assign datad_w = din3;
+
+function lut_data;
+input [15:0] mask;
+input dataa, datab, datac, datad;
+reg [7:0] s3;
+reg [3:0] s2;
+reg [1:0] s1;
+ begin
+ s3 = datad ? mask[15:8] : mask[7:0];
+ s2 = datac ? s3[7:4] : s3[3:0];
+ s1 = datab ? s2[3:2] : s2[1:0];
+ lut_data = dataa ? s1[1] : s1[0];
+ end
+endfunction
+
+always @(dataa_w or datab_w or datac_w or datad_w) begin
+ combout_rt = lut_data(lut_function, dataa_w, datab_w,
+ datac_w, datad_w);
+end
+assign dout = combout_rt & 1'b1;
+endmodule
+
+module DFF (output q,
+ input d, ck);
+ reg q;
+ always @(posedge ck)
+ q <= d;
+
+endmodule
+
+
+
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_achronix.cc
index 8158c56fd..1dc6bdb2f 100755
--- a/techlibs/achronix/synth_speedster.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -25,14 +25,14 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-struct SynthIntelPass : public ScriptPass {
- SynthIntelPass() : ScriptPass("synth_speedster", "synthesis for Acrhonix Speedster22i FPGAs.") { }
+struct SynthAchronixPass : public ScriptPass {
+ SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
- virtual void help() YS_OVERRIDE
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" synth_speedster [options]\n");
+ log(" synth_achronix [options]\n");
log("\n");
log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
log("\n");
@@ -52,7 +52,7 @@ struct SynthIntelPass : public ScriptPass {
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@@ -63,7 +63,7 @@ struct SynthIntelPass : public ScriptPass {
string top_opt, family_opt, vout_file;
bool retime, flatten;
- virtual void clear_flags() YS_OVERRIDE
+ void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
vout_file = "";
@@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass {
flatten = true;
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@@ -95,8 +95,8 @@ struct SynthIntelPass : public ScriptPass {
run_to = args[argidx].substr(pos+1);
continue;
}
- if (args[argidx] == "-flatten") {
- flatten = true;
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
continue;
}
if (args[argidx] == "-retime") {
@@ -108,9 +108,9 @@ struct SynthIntelPass : public ScriptPass {
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
- log_header(design, "Executing SYNTH_SPEEDSTER pass.\n");
+ log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
log_push();
run_script(design, run_from, run_to);
@@ -118,11 +118,11 @@ struct SynthIntelPass : public ScriptPass {
log_pop();
}
- virtual void script() YS_OVERRIDE
+ void script() YS_OVERRIDE
{
if (check_label("begin"))
{
- run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v");
+ run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -146,26 +146,26 @@ struct SynthIntelPass : public ScriptPass {
run("opt -undriven -fine");
run("dffsr2dff");
run("dff2dffe -direct-match $_DFF_*");
- run("opt -full");
+ run("opt -fine");
run("techmap -map +/techmap.v");
- run("opt -fast");
+ run("opt -full");
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
- run("abc -markgroups -dff", "(only if -retime)");
+ run("abc -markgroups -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
{
- run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
run("clean");
}
if (check_label("map_cells"))
{
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
- run("techmap -map +/achronix/speedster22i/cells_map_speedster.v");
- run("dffinit -ff dffeas Q INIT");
+ run("techmap -map +/achronix/speedster22i/cells_map.v");
+ // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
run("clean -purge");
}
@@ -179,10 +179,10 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("vout"))
{
if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s",
+ run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
}
-} SynthIntelPass;
+} SynthAchronixPass;
PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 01:03:59 +0000