diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/miter.cc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1f64c0216..8f27c4c6f 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -144,8 +144,16 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: { if (gold_cross_ports.count(gold_wire)) { - RTLIL::Wire *w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); gold_cell->setPort(gold_wire->name, w); + if (flag_ignore_gold_x) { + RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w)); + for (int i = 0; i < GetSize(w); i++) + miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]); + RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x); + RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x)); + w = miter_module->And(NEW_ID, w_any, w_masked); + } gate_cell->setPort(gold_wire->name, w); continue; } |